Phase locked loop device and method thereof
AssigneeFreescale Semiconductor, Inc.
InventorsGayathri A. Bhagavatheeswaran, Joseph P. Gergen, Arvind Raman, Hector Sanchez
Life of this patent
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Abstract
A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.
Claims20
A method, comprising:
- receiving a reference clock signal at a first phase lock loop;
- in response to determining a first phase difference between a reference clock signal and an output clock signal of the first phase lock loop exceeds a first threshold, asserting a first indicator;
- in response to determining the first phase difference exceeds a second threshold, asserting a second indicator different from the first indicator;
- providing the output clock signal of the first phase lock loop to a first device;
- in response to assertion of the first indicator, providing a first clock signal to the first device;
- and
- in response to assertion of the second indicator, providing a second clock signal to the first device.
A method, comprising:
- receiving a reference clock signal at a first lock loop;
- in response to determining a first phase difference between a reference clock signal and an output clock signal of the first phase lock loop exceeds a first threshold for a first amount of time, asserting a first indicator;
- in response to determining the first phase difference exceeds the first threshold for a second amount of time, asserting a second indicator different from the first indicator;
- providing the output clock signal of the first phase lock loop to a first device;
- in response to assertion of the first indicator, providing a first clock signal to the first device;
- and
- in response to assertion of the second indicator, providing a second clock signal to the first device.
A device, comprising:
- a phase lock loop comprising an input to receive a reference clock signal, a first output of the phase lock loop to provide an output clock signal, and a second output of the phase lock loop to provide a phase difference signal indicative of a first phase difference between the reference clock signal and the output clock signal;
- and
- a compare module comprising an input coupled to the second output of the phase lock loop, a first output of the compare module configured to provide an asserted signal in response to the first phase difference exceeding a first threshold and a second output of the compare module configured to provide an asserted signal in response to the first phase difference exceeding a second threshold;
- a first clock signal provided to a first device in response to an indication of the first phase difference exceeding a first threshold;
- and
- a second clock signal provided to the first device in response to an indication of the phase difference exceeding a second threshold.
Dependencies are inferred from the claim text.