Direct memory access engine physical memory descriptors for multi-media demultiplexing operations
AssigneeIntel Corporation
InventorsDaniel Nemiroff, Balaji Vembu, Raul Gutierrez, Suryaprasad Kareenahalli
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Abstract
The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.
Claims18
An apparatus comprising:
- a plurality of multimedia processing pipeline stages comprising an input engine to copy input data from a described location in a system and produce descriptors, a processing engine to process the input data and prepare descriptors, and an output engine to output data to the described location in the system, each stage to consume a unit of work from its input buffer only when there is space available in its output buffer and each stage writes its output to memory and the next stage to consume its data from memory;
- a plurality of circular buffers corresponding to the plurality of multimedia pipeline stages, wherein a pipeline stage stalls if the circular buffer of a subsequent stage is full, wherein descriptors utilized for passing data between buffers are re-used.
A method comprising:
- identifying a stream of multimedia data to decode, the stream of multimedia data including at least segmented audio data, video data, and application data;
- receiving the stream of multimedia data with a pipelined decoder mechanism having a plurality of processing pipeline stages comprising an input engine to copy input data from a described location in a system and produce descriptors, a processing engine to process the input data and prepare descriptors, and an output engine to output data to the described location in the system;
- demultiplexing the stream of multimedia data with one or more of the pipeline stages, wherein a pipeline stage stalls if the circular buffer of a subsequent stage is full, wherein descriptors utilized for passing data between buffers are re-used and each stage writes its output to memory and the next stage to consume its data from memory;
- and
- transmitting the demultiplexed multimedia segments to processing components for audio data, video data and application independently and securely.
An article comprising a non-transitory computer-readable medium, the computer-readable medium having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to:
- identify a stream of multimedia data to decode, the stream of multimedia data including at least segmented audio data, video data, and application data;
- receive the stream of multimedia data with a pipelined decoder mechanism having a plurality of processing pipeline stages comprising an input engine to copy input data from a described location in a system and produce descriptors, a processing engine to process the input data and prepare descriptors, and an output engine to output data to the described location in the system;
- demultiplex the stream of multimedia data with one or more of the pipeline stages, wherein a pipeline stage stalls if the circular buffer of a subsequent stage is full, wherein descriptors utilized for passing data between buffers are re-used and each stage writes its output to memory and the next stage to consume its data from memory;
- and
- transmit the demutliplexed multimedia segments to processing components for audio data, video data and application independently and securely.
Dependencies are inferred from the claim text.