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US 8,509,094 B2Granted
Edge-based loss-of-signal detection
AssigneeRambus Inc.
InventorsAndrew M. Fuller, John W. Poulton
Life of this patent
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Abstract
Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data.
Claims27
A loss-of-signal (LOS) detector, comprising:
- at least one sampler to sample data bits carried by an incoming data signal and to sample the incoming data signal at a time between two consecutive data bits;
- and
- circuitry to determine based on outputs of the at least one sampler whether an edge glitch has occurred between the two consecutive data bits and to generate a LOS signal based on the determination.
A loss-of-signal detector, comprising:
- means for sampling data bits carried by an incoming data signal and for sampling the incoming data signal at a time between two consecutive data bits;
- and
- means for determining whether an edge glitch has occurred between the two data bits and for generating a LOS signal based on the determination.
A receiver, comprising:
- a clock and data recovery (CDR) circuit having
- at least one sampler to sample data bits carried by an incoming data signal and to sample the incoming data signal at a time in between two consecutive data bits, and
- a locked-loop circuit to generate a recovered clock in dependence on samples produced by the at least one sampler;
- and
- circuitry to determine based on outputs of the at least one sampler whether an edge glitch has occurred between the two consecutive data bits and to generate an LOS signal based on the determination.
2 more elements
A loss-of-signal (LOS) detector, comprising:
- at least one first sampler to sample an incoming data signal within unit intervals corresponding to data bits, to generate data samples;
- a second sampler to sample the incoming data signal at transitions between the unit intervals;
- circuitry to determine when two consecutive bits of the data bits have a like state;
- circuitry to determine when a sample from the second sampler between the consecutive bits has a state that is different from the like state;
- and
- circuitry to generate a LOS signal in dependence on the determination that the sampler from the second sampler has the state that is different from the like state.
3 more elements
An integrated circuit, comprising:
- at least one first sampler to sample an incoming data signal within unit intervals corresponding to data bits, to generate data samples;
- a second sampler to sample the incoming data signal at transitions between the unit intervals;
- loss-of-signal (LOS) detector circuitry to determine when the two consecutive bits of the data bits have a like state, to determine when a sample from the second sampler between the consecutive bits having the like state corresponds to a state different from the like state, and to generate an LOS signal in dependence on the determination that the sampler from the second sampler has the state that is different from the like state;
- and
- clock and data recovery (CDR) circuitry to determine when the two consecutive bits of the data bits have unlike states and to update a recovered clock in dependence on a sample from the second sampler between the consecutive bits having the unlike states.
2 more elements
Dependencies are inferred from the claim text.