Bufferless routing in on-chip interconnection networks
AssigneeMicrosoft Corporation
InventorsThomas Moscibroda, Onur Mutlu
Life of this patent
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AssigneeMicrosoft Corporation
InventorsThomas Moscibroda, Onur Mutlu
Estimating the term…
As microprocessors incorporate more and more devices on a single chip, dedicated buses have given way to on-chip interconnection networks (“OCIN”). Routers in a bufferless OCIN as described herein rank and prioritize flits. Flits traverse a productive path towards their destination or undergo temporary deflection to other non-productive paths, without buffering. Eliminating the buffers of on-chip routers reduces power consumption and heat dissipation while freeing up chip surface area for other uses. Furthermore, bufferless design enables purely local flow control of data between devices in the on-chip network, reducing router complexity and enabling reductions in router latency. Router latency reductions are possible in the bufferless on-chip routing by using lookahead links to send data between on-chip routers contemporaneously with flit traversals.
A method of deflection routing in an on-chip interconnection network having one or more on-chip routers, the method comprising:
A system that includes an on-chip interconnection network, the on-chip interconnection network to perform acts comprising:
A memory device including instructions that are executable by processing logic to perform acts comprising:
A method of local flow control of flow control digits (flits) in an on-chip interconnection network, the method comprising:
Dependencies are inferred from the claim text.