Word line boost circuit
AssigneeeMemory Technology Inc.
InventorsYu-Hsiung Tsai, Po-Hao Lee
Life of this patent
Estimating the term…
Abstract
A word line boost circuit including a first address transfer detector, a second address transfer detector and a boost operation unit is provided. The first address transfer detector generates a first detection pulse in response to variation of a row address signal. The second address transfer detector generates a second detection pulse in response to variation of a column address signal. Moreover, the boost operation unit generates a selection voltage by using a boost voltage according to the first detection pulse, and determines whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse.
Claims20
A word line boost circuit, comprising:
- a first address transfer detector, generating a first detection pulse in response to variation of a row address signal;
- a second address transfer detector, generating a second detection pulse in response to variation of a column address signal;
- and
- a boost operation unit, generating a selection voltage by using a boost voltage according to the first detection pulse, and determining whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse.
A word line boost circuit, comprising:
- a first address transfer detector, determining whether or not to generate a first detection pulse according to a row address signal;
- a second address transfer detector, determining whether or not to generate a second detection pulse according to a column address signal;
- and
- a boost operation unit, switching a selection voltage to a boost voltage according to the first detection pulse, and determining whether or not to switch the selection voltage to the boost voltage according to a delay time between the first detection pulse and the second detection pulse.
A word line boost circuit for boosting a boost voltage in a memory array which designates a selected memory cell by a word line address and a bit line address, comprising:
- a first address transfer detector for detecting variation of the word line address;
- a second address transfer detector for detecting variation of the bit line address;
- and
- a boost operation unit, generating a boost clock signal according to the detected results of the first address transfer detector and the second address transfer detector wherein the boost clock is disabled when the selected memory cell is designated at the same word line address.
Dependencies are inferred from the claim text.