Data processing system

An apparatus comprising:

• a first semiconductor device;
• and
• a second semiconductor device coupled to each other,
• the first semiconductor device comprising a plurality of memory blocks, each including a plurality of memory cells;
• the second semiconductor device comprising a control circuit that is configured to issue an access request to the first semiconductor device with supplying the first semiconductor device with command information and burst operation mode information simultaneously with each other, the command information designating a data read or a data write operation, and the burst operation mode information including a burst length that designates a first number of data that are to be transferred in series between the first and second semiconductor devices and a block selection that designates one of the memory blocks of the first semiconductor device as a start block, and
• the first semiconductor device further comprising:
• a set of first terminals coupled to the second semiconductor device to receive the command information and the burst operation mode information simultaneously with each other;
• a second terminal coupled to the second semiconductor device to transfer the first number of data in series between the first and second semiconductor devices;
• and
• a data access circuit coupled to the memory blocks, the set of first terminals and the second terminal, the data access circuit being configured to access, when the first number is not greater than a second number, the first number of memory cells each included in the start block of the memory blocks in parallel to each other, and to access, when the first number is greater than the second number, the second number of memory cells each included in the start block of the memory blocks in parallel to each other and a third number of memory cells each included in remaining one or ones of the memory blocks in parallel to each other, the third number being the first number minus the second number,
• wherein:
• when the first number is not greater than the second number, the first number of data, that are to be transferred in series between the first and second semiconductor devices, are read out from or written into the first number of memory cells each included in the start block of the memory blocks, and
• when the first number is greater than the second number, the first number of data, that are to be transferred in series between the first and second semiconductor devices, are read out from or written into the second number of memory cells each included in the start block of the memory blocks and the third number of memory cells each included in the remaining block or blocks of the memory blocks.

An apparatus comprising:

• a memory cell array including a plurality of word lines, a plurality bit lines and a plurality of memory cells each connected to associated ones of the word and bit lines, one of the word lines being selected in response to an access request as a selected word line, plural ones of the memory cells that are connected to the selected word line being selected as selected memory cells, the bit lines that are connected respectively to the selected memory cells being divided into first and second bit line blocks each including corresponding ones of the bit lines;
• a plurality of data lines, the data lines being divided into first and second data line groups each including corresponding ones of the data lines, the data lines belonging to the first data line group being smaller in number than the bit lines belonging to the first bit line block, the data lines belonging to the second data line group being smaller in number than the bit lines belonging to the second bit line block;
• a column switch circuit supplied with block selection information and configured to electrically connect designated ones of the bit lines belonging to the first bit line block to the data lines belonging to the first data line group, respectively, with electrically disconnecting the bit lines belonging to the second bit line block from the data lines belonging to the second data line group, when the block selection information takes a first state to represent a first burst length, and to electrically connect the designated ones of the bit lines belonging to the first bit line block to the data lines belonging to the first data line group, respectively, and designated ones of the bit lines belonging to the second bit line block to the data lines belonging to the second data line group, respectively, when the block selection information takes a second state to represent a second burst length that is greater than the first burst length;
• a data terminal;
• a serializing circuit electrically coupled between the data terminal and the first and second data line groups, the serializing circuit being configured to respond to the first burst length to perform a first parallel-to-serial conversion operation in which first data signals supplied in parallel to the first data line group from the first bit line block through the column switch circuit are transferred in series to the data terminal and to respond to the second burst length to perform a second parallel-to-serial conversion operation in which second data signals supplied in parallel to the first and second data line groups from the first and second bit line blocks through the column switch circuit are transferred in series to the data terminal;
• and
• a de-serializing circuit electrically coupled between the data terminal and the first and second data line groups, the de-serializing circuit being configured to respond to the first burst length to perform a first serial-to-parallel conversion operation in which third data signals supplied in series from the data terminal are transferred in parallel to the first data line group and to respond to the second burst length to perform a second serial-to-parallel conversion operation in which fourth data signals supplied in series from the date terminal are transferred in parallel to the first and second data line groups, the third data signals being conveyed from the data lines belonging to the first data line group to the bit lines belonging to the first bit line block through the column switch circuit, respectively, and the fourth data signals being conveyed from the data lines belonging to the first and second data line groups to the bit lines belonging to the first and second bit line blocks through the column switch circuit, respectively.