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US 8,509,018 B2Granted
Sense amplifier with adjustable back bias
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorAtul Katoch
Life of this patent
Estimating the term…
Abstract
A circuit having a sensing circuit and at least one of a first node and a second node is described. The sensing circuit includes a pair of a first type transistors and a pair of a second type transistors. Each transistor of the pair of the first type transistors is coupled in series with a transistor of the pair of the second type transistors. The first node has a first voltage and is coupled to each bulk of each transistor of the pair of the first type transistors. The second node has a second voltage and is coupled to each bulk of each transistor of the pair of the second type transistors.
Claims20
A circuit comprising:
- a sensing circuit including
- a pair of a first type transistors;
- a pair of a second type transistors;
- each transistor of the pair of the first type transistors coupled in series with a transistor of the pair of the second type transistors;
- and
- at least one of
- a first node having a first voltage and coupled to each bulk of each transistor of the pair of the first type transistors, wherein the first voltage is lowered when the sensing circuit is on and the first type transistors are P-type transistors;
- or
- a second node having a second voltage and coupled to each bulk of each transistor of the pair of the second type transistors, wherein the second voltage is raised when the sensing circuit is on and the second type transistors are N-type transistors.
6 more elements
A method comprising:
- setting each of a first bit line, a second bit line, a first voltage supply line, and a second voltage supply line to a first voltage level;
- enabling a memory cell electrically coupled to the first bit line to share charge with the first bit line;
- thereby causing a voltage difference between the first bit line and the second bit line to develop;
- changing a voltage level at bulks of a pair of transistors in a sensing pair to a first bulk level, thereby causing a change in a threshold voltage of the pair of transistors, wherein the changing the voltage level comprises raising the voltage level at the bulks if the pair of transistors are N-type transistors and lowering the voltage level at the bulks if the pair of transistor are P-type transistors;
- setting the first voltage supply line and the second voltage supply line to a first supply level and a second supply level, respectively;
- thereby causing the voltage difference to develop further;
- and
- changing the voltage level at the bulks of the pair of transistors to a second bulk level.
5 more elements
A circuit comprising:
- a pair of data lines having a first data line and a second data line;
- a sensing pair including
- a first PMOS transistor having a first PMOS source, a first PMOS drain, a first PMOS gate, and a first PMOS bulk;
- a second PMOS transistor having a second PMOS source, a second PMOS drain, a second PMOS gate, and a second PMOS bulk;
- a first NMOS transistor having a first NMOS source, a first NMOS drain, a first NMOS gate, and a first NMOS bulk;
- and
- a second NMOS transistor having a second NMOS source, a second NMOS drain, a second NMOS gate, and a second NMOS bulk;
- the first PMOS gate coupled to the first NMOS gate and to the first data line;
- the first PMOS drain coupled to the first NMOS drain and to the second data line;
- the second PMOS gate coupled to the second NMOS gate and to the second data line;
- the second PMOS drain coupled to the second NMOS drain and to the first data line;
- an operation voltage source coupled to the first PMOS source and the second PMOS source;
- a ground voltage source coupled to the first NMOS source and the second NMOS source;
- a first node having a first voltage and coupled to the first PMOS bulk and the second PMOS bulk;
- a second node having a second voltage and coupled to the first NMOS bulk and the second NMOS bulk, wherein when the sensing pair is turned on, the first voltage is lowered or the second voltage is raised;
- and
- a memory cell coupled to a data line of the pair of data lines.
14 more elements
Dependencies are inferred from the claim text.