Memory device and related operating methods
AssigneeAdvanced Micro Devices, Inc.
InventorMichael Dreesen
Life of this patent
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Abstract
A memory device is provided that includes a memory cell, a voltage input, a plurality of bit lines, an amplifier connected to only a particular one of the bit lines, and a switch that is coupled to the amplifier and the voltage input. The switch is configured to prevent the voltage input from being electrically coupled to the amplifier when the plurality of bit lines are electrically floating.
Claims18
A method of operating a memory device that comprises a memory cell, a power supply voltage input, a plurality of bit lines directly coupled to the memory cell, pre-charge circuitry coupled to the memory cell by the plurality of bit lines, and a single-ended sense amplifier coupled to the power supply voltage input and to one of the plurality of bit lines, the method comprising:
- controlling the pre-charge circuitry to allow the plurality of bit lines to electrically float during a floating bit line mode of operation;
- and
- preventing the power supply voltage input from being supplied to the single-ended sense amplifier during the floating bit line mode of operation.
A memory device, comprising:
- a memory cell;
- a power supply voltage input;
- a plurality of bit lines directly coupled to the memory cell;
- pre-charge circuitry coupled to the memory cell by the plurality of bit lines, wherein the pre-charge circuitry is controllable to leave the plurality of bit lines electrically floating during a floating bit line mode of operation;
- a single-ended sense amplifier coupled to the power supply voltage input and to one of the plurality of bit lines;
- and
- a first switch coupled between the single-ended sense amplifier and the power supply voltage input, wherein the first switch is controllable to prevent the power supply voltage input from being electrically coupled to the single-ended sense amplifier during the floating bit line mode of operation.
A memory device, comprising:
- a memory cell;
- a voltage input;
- a plurality of bit lines directly coupled to the memory cell;
- an amplifier directly connected to only a particular one of the bit lines;
- and
- a switch, coupled to the amplifier and the voltage input, and being configured to prevent the voltage input from being electrically coupled to the amplifier when the plurality of bit lines are electrically floating.
Dependencies are inferred from the claim text.