Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsVolodymyr Shvydun, Saman M. I. Adham
Life of this patent
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Abstract
Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. By performing obvious repair during collection of the FBM data, testing and date storage resources can be saved. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. The compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited.
Claims20
A method of self-testing and self-repairing a random access memory (RAM), comprising:
- collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures;
- and wherein the RAM is divided into a number of segments;
- performing obvious repair of failed cells during the collecting of the failure data;
- analyzing the failure data in the two FBM data structure to determine repair methods;
- and
- repairing failed cells of the RAM by using the redundant rows and columns until either all failed cells are repaired or the redundant rows and columns are all used.
A method of self-testing and self-repairing a random access memory (RAM), comprising:
- collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures;
- and wherein the RAM is divided into a number of segments, wherein a first FBM data structure includes a column for row address and a plurality of columns for error flags, and wherein a second FBM data structure includes a plurality of columns for column indexes corresponding to column addresses of failed cells;
- performing obvious repair of failed cells during the collecting of the failure data;
- analyzing the failure data in the two FBM data structure to determine repair methods;
- and
- repairing failed cells of the RAM by using the redundant rows and columns until either all failed cells are repaired or the redundant rows and columns are all used.
A memory array with a built-in self-test (BIST) module and a built-in self-repair (BISR) module to repair a main memory of the memory array, comprising:
- the main memory;
- a first number of redundant rows for row repair of the main memory;
- a second number of redundant columns for column repair of the main memory, and wherein the main memory is evenly divided into the second number of segments and each redundant column is assigned for column repair in an assigned segment;
- the BIST module for testing the main memory;
- and
- the BISR module for repairing the main memory by using the redundant rows and redundant columns, wherein the BISR module performs obvious repair during testing of the main memory, and wherein the BISR instructs the BISR to stop testing untested portion of columns and rows repaired by obvious repairs, and wherein the BISR module performs other repairs based on failure bit maps (FBMs) generated from testing the entire main memory.
Dependencies are inferred from the claim text.