Back to results
US 8,509,013 B1Granted
Partitioned bitline for memory
AssigneeMicron Technology, Inc.
InventorRaed Sabbah
Life of this patent
Estimating the term…
Abstract
Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.
Claims16
A memory device comprising:
- a first sub-array of memory cells which are addressable via a first bitline;
- a second sub-array of memory cells which are addressable via a second bitline;
- a sense amplifier to receive amplified signals from said first bitline;
- and
- a sense amplifier repeater (SAR) circuit electronically interconnecting said first and second sub-arrays, said SAR circuit configured to amplify signals on said second bitline resulting from a process of reading from said second sub-array to generate amplified signals, and to place said amplified signals onto said first bitline, wherein the sense amplifier is further configured to amplify the amplified signals.
2 more elements
A method of accessing memory, the method comprising:
- determining whether a memory access request is addressed to a first sub-array of memory cells which are addressable via a first bitline or a second sub-array of memory cells which are addressable via a second bitline;
- upon a determination that said memory access request is addressed to said second sub-array, activating a first sense amplifier to receive first signals from said first bitline and activating a second sense amplifier to receive second signals from said second bitline, wherein said second signals result from a process of reading from said second sub-array;
- upon a determination that said memory access request is addressed to said first sub-array, activating said first sense amplifier to receive said first signals from said first bitline and de-activating said second sense amplifier;
- and
- upon a determination that said memory access request is addressed to said second sub-array:
- amplifying said second signals using said second sense amplifier;
- placing said amplified second signals onto said first bitline;
- and
- further amplifying said amplified second signals.
6 more elements
A system comprising:
- a memory controller configured to operate a memory device, said memory device comprising:
- a first sub-array of memory cells which are addressable via a first bitline;
- a second sub-array of memory cells which are addressable via a second bitline;
- a first sense amplifier configured to receive amplified signals from said first bitline;
- and
- a sense amplifier repeater (SAR) circuit electronically interconnecting said first and second sub-arrays, said SAR circuit configured to amplify signals on said second bitline resulting from a process of reading from said second sub-array to generate amplified signals, and to place said amplified signals onto said first bitline, wherein the sense amplifier is further configured to amplify the amplified signals;
- and
- a processor configured to host one or more applications and to initiate said process of reading from said second sub-array.
5 more elements
Dependencies are inferred from the claim text.