Precharge signal generation circuit of semiconductor memory apparatus
AssigneeSK hynix Inc.
InventorJae Bum Ko
Life of this patent
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Abstract
A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address.
Claims14
A precharge signal generation circuit of a semiconductor memory apparatus, comprising:
- a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command;
- and
- a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address.
A precharge signal generation circuit of a semiconductor memory apparatus, comprising:
- a first delay pass configured to delay a precharge command by first delay time in response to a control signal and a clock signal;
- a second delay pass configured to delay a bank column address strobe signal by a delay time, which is substantially identical to the first delay time, in response to the precharge command delayed in the first delay pass in a unit manner, and generate a bank column address strobe signal;
- a signal combination part configured to combine the precharge command delayed in the unit manner with a write flag signal for defining a write operation to generate a write precharge command, and combine the bank column address strobe signal with the write flag signal to generate a write bank precharge address;
- and
- a decoder configured to generate a precharge signal in response to the read precharge command and the write bank precharge address.
Dependencies are inferred from the claim text.