Command paths, apparatuses, memories, and methods for providing internal commands to a data path

A memory, comprising:

• a command receiver configured to receive a command and provide an internal command signal;
• a latency shift circuit coupled to the command receiver to receive the internal command signal, the latency shift circuit configured to add a delay in providing the internal command signal responsive to a clock signal, the delay based at least in part on a shift count;
• a timing calibration circuit coupled to the latency shift circuit and configured to proved the shift count, the shift count based at least in part on a latency and a modeled path delay of the command path;
• a clock path configured to receive a clock signal and responsive thereto provide the internal clock signal;
• and
• a data path coupled to the clock path, the data path configured to receive data and provide the same for writing to a memory responsive to the internal clock signal.

A method for providing an internal command to a data path, the method comprising:

• receiving a command;
• propagating the command through a command path to provide an internal command;
• receiving data;
• propagating the data through a data path;
• determining a difference between a latency value and a path delay difference, the path delay difference representing a modeled path delay difference between the command path and the data path measured in terms of a number of clock periods;
• delaying the propagation of the command through the command path to the data path by a delay based at least in part on the difference between the latency value and the path delay difference;
• and
• providing the internal command to the data path responsive to an internal clock signal.