Hybrid read scheme for multi-level data
AssigneeInfineon Technologies AG
InventorsThomas Nirschl, Nigel Chan, Jan Otterstedt
Life of this patent
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Abstract
Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal SRef to a first reference value to induce determination of a first comparison result. At a second subsequent time in the read operation, the state machine sets the reference signal SRef to a second reference value, which is based on the first comparison result. Setting the reference signal to the second reference value induces determination of a second comparison result. The first and second comparison results are then used to determine the digital value read from the memory cell.
Claims21
A method of reading a data state stored in a multi-state memory cell configured to store at least three data states therein, wherein respective neighboring data states are separated by respective guard bands, the method comprising:
- providing a read signal from the cell, where the read signal is indicative of a to-be-determined data state corresponding to one of the at least three data states stored in the memory cell;
- setting a reference signal to a first, predetermined reference value corresponding to a first guard band;
- comparing the read signal to the first, predetermined reference value to obtain a first comparison result;
- setting the reference signal to a second reference value, which corresponds to a higher or lower guard band relative to the first guard band, based on the first comparison result;
- comparing the read signal to the second reference value to ascertain a digital value of the to-be-determined data state read from the memory cell.
A memory device, comprising:
- a memory cell including a multi-level data storage element configured to store more than two data states therein;
- a bitline coupled to the multi-level data storage element and configured to carry a read signal there from, where the read signal is indicative of a to-be-determined data state read from the memory cell;
- a sense amp coupled to the bitline and configured to provide comparison results which are based on respective comparisons between a reference signal and the read signal during a read operation;
- and
- a control circuit to, at a first time in the read operation, set the reference signal to a first reference value to induce determination of a first comparison result, and to, at a second subsequent time in the read operation, set the reference signal to a second reference value based on the first comparison result to induce determination of a second comparison result.
A memory device, comprising:
- a memory cell including a multi-level data storage element configured to store more than two data states therein, wherein the multi-level data storage element comprises:
- a first, control terminal on which a control voltage is provided and second and third terminals between which a current is measured, wherein the current is dependent on the control voltage and a to-be-determined data state stored in the multi-level data storage element;
- a bitline coupled to the second terminal of the multi-level data storage element;
- a sense amp coupled to the bitline and configured to provide comparison results which are based on respective comparisons between a reference current signal and the current read from the multi-level data storage element during a read operation;
- and
- a control circuit to, at a first time in the read operation, set the reference current signal to a first reference current value to induce determination of a first comparison result, and to, at a second subsequent time in the read operation, set the reference current signal to a second reference current value based on the first comparison result to induce determination of a second comparison result.
A method of ascertaining a to-be-determined data state from a multi-level data storage element having a first control terminal and second and third terminals, the method comprising:
- applying a first control voltage to the control terminal and concurrently measuring a first read current across the second and third terminals, where the first read current is indicative of the to-be-determined data state;
- comparing the first read current to a first predetermined reference current, which corresponds to a first guard band, to obtain a first comparison result;
- applying a second control voltage to the control terminal and concurrently measuring a second read current across the second and third terminals, wherein the second read current is indicative of the to-be-determined data state;
- comparing the second read current to a second predetermined reference current, which corresponds to a higher or lower guard band relative to the first guard band, to obtain a second comparison result, where the second predetermined reference current has a current level that is set based on the first comparison result;
- ascertaining the to-be-determined data state based on the first and second comparison results.
Dependencies are inferred from the claim text.