Semiconductor device and method of detecting abnormality on semiconductor device
AssigneeRenesas Electronics Corporation
InventorJunichi Yamada
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes: a plurality of word lines; a word line driver; a first detection circuit; and a control circuit. The plurality of word lines is connected to gates of a plurality of memory cell transistors, respectively. The word line driver supplies one of a selection voltage and a non-selection voltage to each of the plurality of word lines. The first detection circuit detects a first current flowing into the word line driver through a wiring supplying the selection voltage when the selection voltage is supplied to one of the plurality of word lines through the word line driver. The control circuit detects abnormality of the plurality of word lines and the word line driver based on the first current.
Claims11
A semiconductor device comprising:
- a plurality of word lines configured to be connected to gates of a plurality of memory cell transistors, respectively;
- a word line driver configured to supply one of a selection voltage and a non-selection voltage to each of said plurality of word lines;
- a first detection circuit configured to detect a first current flowing into said word line driver through a wiring supplying said selection voltage when said selection voltage is supplied to one of said plurality of word lines through said word line driver;
- a control circuit configured to detect abnormality of said plurality of word lines and said word line driver based on said first current;
- and
- a second detection circuit configured to detect a second voltage of said plurality of word lines when said word line driver supplies said non-selection voltage to said plurality of word lines,
- wherein said control circuit detects abnormality of said plurality of word lines and said word line driver based on the first current and said second voltage.
A method of detecting abnormality on a semiconductor device including a plurality of memory cell transistors, comprising:
- supplying, through a word line driver which supplies one of a selection voltage and a non-selection voltage to each of a plurality of word lines connected to gates of said plurality of memory cell transistors, respectively, said selection voltage to one of said plurality of word lines;
- detecting a first current flowing into said word line driver through a wiring supplying said selection voltage;
- detecting abnormality of said plurality of word lines and said word line driver based on said first current, and
- detecting a second voltage of said plurality of word lines when said word line driver supplies said non-selection voltage to said plurality of word lines,
- wherein said step of detecting said abnormality includes:
- detecting abnormality of said plurality of word lines and said word line driver based on the first current and said second voltage.
Dependencies are inferred from the claim text.