Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit

A logic circuit comprising:

• a master latch configured to latch input data;
• and
• a slave latch configured to latch output data of the master latch, wherein the slave latch includes a nonvolatile logic circuit, the nonvolatile logic circuit including,
• a latch unit including a pair of first and second latch nodes;
• and
• a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively, wherein
• a write operation is performed on the first and second nonvolatile memory cells by supplying current to the first and second nonvolatile memory cells in different directions when a write enable signal is activated, the direction of flow of current being determined based on a logic value of data stored on the respective first and second latch nodes, and
• a logic value stored in the first nonvolatile memory cell is different from a logic value stored in the second nonvolatile memory cell.

An integrated circuit comprising:

• a plurality of circuit blocks including at least one logic circuit block and at least one nonvolatile logic circuit, the at least one nonvolatile logic circuit including,
• a latch unit including a pair of first and second latch nodes, and
• a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively;
• a power sensor configured to generate a sense signal when a value of a power supplied to at least one of the plurality of circuit blocks is less than or equal to a threshold value;
• and
• a controller configured to generate a read enable signal or the write enable signal based on the sense signal generated by the power sensor or an external command, wherein,
• the first and second latch nodes of the nonvolatile logic circuit are configured to latch an output data of the at least one logic circuit block or an external input data,
• a write operation is performed on the first and second nonvolatile memory cells by supplying current to the first and second nonvolatile memory cells in different directions when a write enable signal is activated, the direction of flow of current being determined based on a logic value of data stored on the respective first and second latch nodes, and
• a logic value stored in the first nonvolatile memory cell is different from a logic value stored in the second nonvolatile memory cell.

A method of operating an integrated circuit including at least one nonvolatile logic circuit and at least one logic circuit block, the at least one nonvolatile logic circuit including a latch unit, the latch unit including a pair of first and second latch nodes and a pair of first and second nonvolatile memory cells, the method comprising:

• generating a sense signal when a value of a power supplied to the at least one logic circuit block is less than or equal to a threshold value;
• generating a read enable signal or a write enable signal based on the sense signal or an external command;
• electrically connecting the first and second nonvolatile memory cells to the first and second latch nodes, respectively, when the write enable signal is activated;
• and
• performing a write operation on the first and second nonvolatile memory cells by supplying current to the first and second nonvolatile memory cells in different directions based on data stored on the respective first and second latch nodes,
• wherein a logic value stored in the first nonvolatile memory cell is different from a logic value stored in the second nonvolatile memory cells.