Vertical NAND memory
AssigneeIntel Corporation
InventorsZengtao Liu, Graham Wolstenholme
Life of this patent
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Abstract
A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND memory cells to the substrate for erase operations. In the second mode, the one or more mid-string devices couple the body of a first stack of NAND memory cells to a body of a second stack of memory NAND memory cells, allowing the two stacks operate as a single NAND string for read and programming operations.
Claims30
A method to control a group of memory cells, the method comprising:
- erasing the group of memory cells, the group of memory cells including a first stack of NAND memory cells sharing a first body constructed on a substrate, and a second stack of NAND memory cells sharing a second body constructed on the substrate, by:
- applying an idle voltage to first control gates of the first stack of NAND memory cells and second control gates of the second stack of NAND memory cells;
- applying an erase voltage to the substrate;
- and
- controlling one or more mid-string devices positioned between the substrate and the first and second stacks of NAND memory cells to allow the erase voltage to propagate to the first body and the second body.
A memory device comprising:
- a first stack of NAND memory cells sharing a first body, the NAND memory cells of the first stack including a first set of control gates, and a first set of charge storage regions located between the first set of control gates and the first body;
- a second stack of NAND memory cells sharing a second body, the NAND memory cells of the second stack including a second set of control gates, and a second set of charge storage regions located between the second set of control gates and the second body;
- and
- one or more mid-string devices positioned between a substrate and the first and second stacks of NAND memory cells, the one or more mid-string devices capable of coupling the substrate to the first and second bodies in a first mode of operation, and capable of coupling the first body to the second body, isolated from the substrate, in a second mode of operation.
An electronic system comprising:
- a processor capable of generating memory control commands;
- and
- at least one memory device coupled to the processor and operating in response to the memory control commands, the at least one memory device comprising:
- a first stack of NAND memory cells sharing a first body, the NAND memory cells of the first stack including a first set of control gates, and a first set of charge storage regions located between the first set of control gates and the first body;
- a second stack of NAND memory cells sharing a second body, the NAND memory cells of the second stack including a second set of control gates, and a second set of charge storage regions located between the second set of control and the second body;
- and
- one or more mid-string devices positioned between a substrate and the first and second stacks of NAND memory cells, the one or more mid-string devices capable of coupling the substrate to the first and second bodies in a first mode of operation, and capable of coupling the first body to the second body, isolated from the substrate, in a second mode of operation.
Dependencies are inferred from the claim text.