Multiple plane, non-volatile memory with synchronized control
AssigneeRambus Inc.
InventorBrent Steven Haukness
Life of this patent
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Abstract
This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the “program phase” and the “verify phase” of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution.
Claims38
A nonvolatile memory apparatus, comprising:
- at least two planes, each plane having
- a plurality of memory cells,
- a buffer to hold data for data transfer for the associated plane, and array control circuitry;
- state logic for each of the planes (a) to apply plural state change cycles to the associated plane and (b) to track at least whether the associated plane is currently undergoing state change operations;
- and
- sequence control circuitry to cause the array control circuitry for each of the at least two planes to concurrently apply a voltage pulse for the associated plane when undergoing state change operations;
- where the non-volatile memory apparatus is to perform state change operations concurrently for the at least two planes, in a manner not necessarily synchronized by cycle number.
A nonvolatile memory device, comprising:
- NAND flash memory cells arranged into at least two planes;
- a buffer for each one of the at least two planes;
- and
- means for applying program-verify cycles across all the planes in a manner constrained to have concurrent voltage pulses for at least one of programming or erasing operations but not necessarily synchronized by cycle number.
A method of operating a nonvolatile memory apparatus, comprising:
- generating a voltage for state change operations;
- distributing the voltage to plural planes of memory, each plane having an associated array of memory cells and a buffer used for data transfer;
- controlling state independently for each one of the plural planes, including tracking at least whether additional program-verify cycles are needed for memory cells within the associated plane to have a desired logic state;
- and
- for planes that are subject to contemporaneous state change operations, using the voltage to perform state change operations.
An apparatus, comprising:
- a plurality of planes of NAND flash memory, each plane having an array of nonvolatile memory cells;
- a buffer for each of the plurality of planes;
- and
- circuitry to apply concurrent voltage pulses to effectuate concurrent state change operations in the plurality of planes;
- where the NAND flash memory integrated circuit is to perform programming using a number of program-verify cycles, and is to perform state change operations concurrently for the at least two planes, in a manner not necessarily synchronized by program-verify cycle number.
A method of operating a nonvolatile memory apparatus, comprising:
- providing nonvolatile memory cells arranged into at least two planes, and a buffer for each of the planes;
- and
- applying voltage pulses to the planes in a manner constrained to be concurrent for a state change operation;
- where the nonvolatile memory cells are flash memory cells, and where applying the voltage pulses includes applying concurrent state change operations across the planes in a manner that is synchronized but not necessarily by program-verify cycle number.
Dependencies are inferred from the claim text.