Method and apparatus of performing an erase operation on a memory integrated circuit

A memory apparatus, comprising:

• a plurality of memory cells;
• a plurality of word lines accessing the plurality of memory cells, the plurality of word lines divided into a plurality of erase groups including a first erase group and a second erase group, the first erase group having two outermost word lines at opposite ends of the first erase group and an inner word line neighboring one of the two outermost word lines;
• a dummy word line located outside the first erase group, the dummy word line neighboring the first erase group,
• wherein a first distance between a first one of the outermost word lines and the dummy word line is greater than a second distance between the first one of the outermost word line and the inner word line.

A memory apparatus, comprising:

• a plurality of memory cells;
• a plurality of word lines accessing the plurality of memory cells, the plurality of word lines divided into a plurality of erase groups including a first erase group and a second erase group, the first erase group having two outermost word lines at opposite ends of the first erase group and an inner word line neighboring one of the two outermost word lines, the second erase group having two outermost word lines at opposite ends of the second erase group;
• a dummy word line located outside the first erase group, the dummy word line neighboring the first erase group,
• wherein a first distance between a first one of the outermost word lines of the first erase group and a first one of the outermost word lines of the second erase group is greater than a second distance between the first one of the outermost word lines of the first erase group and the inner word line of the first erase group.