Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsHiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Masanori Hayashikoshi
Life of this patent
Estimating the term…
Abstract
A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.
Claims10
A semiconductor device comprising a memory array, in which a memory cell for magnetically storing a data signal is arranged in a matrix, the memory array being divided into
- a plurality of segments for each predetermined number of columns, each segment being further divided into blocks for each row, the semiconductor device further comprising:
- a digit line provided for each block;
- a plurality of bit lines provided corresponding to each column;
- a plurality of digit line drivers each causing a magnetizing current to flow through the digit line of one selected block;
- a bit line driver which causes a write current to flow in a direction corresponding to a logic of a data signal to a bit line in a selected segment and writes the data signal to a memory cell of the selected block;
- and a decoder which, when an address of one segment has been input from the outside, selects one segment corresponding to the address and couples the selected segment to either one of the digit line drivers, and which, when addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to different digit line drivers.
A semiconductor device comprising a memory array, in which a memory cell for magnetically storing a data signal is arranged in a matrix, the memory array being divided into a plurality of segments for each predetermined number of columns, each segment being further divided into blocks for each row, the semiconductor device further comprising:
- a digit line provided for each block;
- a plurality of bit lines provided corresponding to each column;
- a digit line driver which causes a magnetizing current to flow through a digit line of a selected block;
- and
- a bit line driver which causes a write current to flow in a direction corresponding to a logic of a data signal to a bit line in a selected segment and writes the data signal to a memory cell of the selected block, wherein
- the digit line driver, when the magnetizing current falls, reduces the magnetizing current at a speed slower than that when the magnetizing current rises.
A semiconductor device comprising a memory array, in which a memory cell for magnetically storing a data signal is arranged in a matrix, the memory array being divided into a plurality of segments for each predetermined number of columns, each segment being further divided into blocks for each row, the semiconductor device further comprising:
- a digit line provided for each block;
- a plurality of bit lines provided corresponding to each column;
- a digit line driver which causes a magnetizing current to flow through a digit line of a selected block;
- and
- a bit line driver which causes a write current to flow in a direction corresponding to a logic of a data signal to a bit line in a selected segment and writes the data signal to a memory cell of the selected block, wherein
- the bit line driver causes the write current to rise, subsequently, the digit line driver causes the magnetizing current to rise, subsequently, the digit line driver causes the magnetizing current to fall, and subsequently, the bit line driver causes the write current to fall.
A semiconductor device comprising a memory array, in which a memory cell for magnetically storing a data signal is arranged in a matrix, the memory array being divided into a plurality of segments for each predetermined number of columns, each segment being further divided into blocks for each row, the semiconductor device further comprising:
- a digit line provided for each block;
- a plurality of bit lines provided corresponding to each column;
- a digit line driver which causes a magnetizing current to flow through a digit line of a selected block;
- and
- a bit line driver which causes a write current to flow in a direction corresponding to a logic of a data signal to a bit line in a selected segment and writes the data signal to a memory cell of the selected block, wherein
- the bit line is formed with a cladding wiring structure, and wherein
- the bit line drivers causes the write current to rise or fall at a speed slower than that when the magnetizing current rises.
Dependencies are inferred from the claim text.