Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorYoshihiro Ueda
Life of this patent
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Abstract
According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target.
Claims16
A semiconductor memory device comprising:
- a first cell array comprising memory cells and reference cells, each of the memory cells comprising a variable resistance element configured to store data on the basis of a change in resistance, each of the reference cells comprising a resistance used to determine data of the memory cell;
- a second cell array located adjacent to the first cell array in a first direction;
- a third cell array located adjacent to the first cell array in a second direction crossing the first direction;
- a fourth cell array located adjacent to the second cell array in the second direction;
- and
- a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell,
- wherein a reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target.
Dependencies are inferred from the claim text.