Resistive storage-based semiconductor memory device

A resistive storage-based semiconductor memory device comprising:

• a plurality of upper interconnections;
• a plurality of lower interconnections;
• a first dummy upper interconnection arranged in a same level as the upper interconnections and having line width larger than that of the upper interconnection;
• memory cells arranged in intersecting positions between the upper interconnections and the lower interconnections, the memory cells being laminated in a direction perpendicular to a substrate surface of a semiconductor substrate into a 3-dimensional structure by alternately laminating the plural upper interconnections and plural lower interconnections;
• first dummy cells arranged in intersecting positions between the first dummy upper interconnection and the lower interconnections;
• and
• a control circuit that applies a first voltage to a selected one of the upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to the first dummy upper interconnection and independently controls the first to third voltages to be set to different values.