US 8,508,971 B2 · Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate

Abstract

A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.

Claims20

Dependent claims

A semiconductor device comprising a plurality of one-time programmable memory cells, each said memory cell comprising:

a dual gate transistor having a channel, a gate dielectric disposed over said channel, a floating gate disposed over said gate dielectric, a floating gate oxide disposed over said floating gate and an upper gate comprising a metal and one of polysilicon and a silicide, disposed over said floating gate oxide and coupled to a first word line;
and
a further transistor having a gate coupled to a second word line, a source coupled to a first bit line and a drain coupled to said floating gate,
said dual gate transistor having a source coupled to a signal line and a drain coupled to one of a second bit line and ground.

1 more element

Dependencies are inferred from the claim text.

Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate

Life of this patent

Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate

Life of this patent

Abstract

Claims20