Semiconductor apparatus
AssigneeHitachi, Ltd.
InventorsMakoto Saen, Kenichi Osada, Masanao Yamaoka, Tomonori Sekiguchi
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Abstract
The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.
Claims4
A semiconductor apparatus comprising:
- a plurality of logic semiconductor chips each including a processor;
- a memory semiconductor chip stacked in a layer above or below the plurality of logic semiconductor chips;
- and
- a plurality of penetration-electrodes,
- wherein a penetration-electrode among the plurality of the penetration-electrodes, for use in establishing communication between the memory semiconductor chip and the plurality of the logic semiconductor chips, is disposed in such a way as to be in a band-like form and in a central region in each of the plurality of logic semiconductor chips and the memory semiconductor chip, and
- wherein penetration-electrodes among the plurality of the penetration-electrodes, for use in establishing communication among the plurality of the logic semiconductor chips, are disposed in a dispersed fashion inside a region of each of the plurality of the logic semiconductor chips.
Dependencies are inferred from the claim text.