3T pixel for CMOS image sensors with low reset noise and low dark current generation utilizing parametric reset
AssigneeIntellectual Ventures II LLC
InventorJaroslav Hynecek
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Abstract
The present invention describes in detail the solid-state image sensor, specifically the image sensors pixel that has three transistors, high sensitivity, low reset noise, and low dark current. Low reset noise is achieved by parametrically changing the voltage dependent capacitance of the charge detection node in such a manner that during reset the charge detection node capacitance is low while during sensing and integration cycles the charge detection node capacitance is high. This feature thus results in high dynamic range, which is important for sensors using very small pixels. The low dark current generation is achieved by quenching the interface states by placing a p+ implant near the silicon-silicon dioxide interface.
Claims12
An image sensor pixel circuit, comprising:
- a photodiode including a charge detection node configured to convert impinging photons into electrons and to provide a large detection node capacitance during sensing of the charge detection node and a low detection node capacitance during reset of the charge detection node;
- a source follower transistor coupled to the charge detection node and configured to sense collected charge;
- and
- a reset transistor coupled to the charge detection node and configured to selectively reset the charge detection node;
- wherein the charge detection node is implemented in STI CMOS technology and comprises a p-type implant layer and an n-type doped poly-silicon layer deposited over a portion of the p-type implant layer to form a direct poly-silicon to silicon contact.
An image sensor pixel circuit, comprising:
- a photodiode including a charge detection node configured to convert impinging photons into electrons;
- an addressing transistor configured to selectively couple the charge detection node to an output in response to an addressing signal;
- and
- a reset transistor configured to selectively reset the charge detection node;
- wherein the photodiode and the charge detection node provide a fixed-value capacitor and a voltage-dependent capacitor;
- wherein low reset noise is configured to be achieved by parametrically changing the capacitance of the voltage-dependent capacitor during a reset cycle such that the detection node capacitance is low during a reset cycle and high during charge-sensing and integration cycles;
- and
- wherein the charge detection node is implemented in STI CMOS technology and comprises a p-type implant layer and an n-type doped poly-silicon layer deposited over a portion of the p-type implant layer to form a direct poly-silicon to silicon contact.
Dependencies are inferred from the claim text.