Image signal processor line buffer configuration for processing ram image data

An image signal processing system comprising:

• an image processing pipeline comprising a raw pixel processing unit, wherein the raw pixel processing unit is configured to process and convert raw pixels acquired using a digital image sensor into corresponding color RGB pixels and comprises a first row of logic and a plurality of line buffers comprising a first subset of line buffers and a second subset of line buffers, wherein the raw pixel processing unit comprises:
• a first gain, offset, and clamping logic implemented using the first row of logic;
• defective pixel correction and detection unit implemented using the first row of logic, the first line buffer, the second line buffer, the third line buffer, and the fourth line buffer;
• noise reduction logic implemented using the first row of logic, the first line buffer, the second line buffer, the third line buffer, the fourth line buffer, the fifth line buffer, the sixth line buffer, the seventh line buffer, the eighth line buffer, the ninth line buffer, and the tenth line buffer;
• lens shading correction logic implemented using the sixth line buffer, the seventh line buffer, the eighth line buffer, the ninth line buffer, and the tenth line buffer;
• a second gain, offset, and clamping logic implemented using the sixth line buffer, the seventh line buffer, the eighth line buffer, the ninth line buffer, and the tenth line buffer;
• and
• demosaicing logic implemented using the sixth line buffer, the seventh line buffer, the eighth line buffer, the ninth line buffer, and the tenth line buffer;
• wherein the first subset of line buffers comprises a first line buffer configured to receive a first output from the first row of logic, a second line buffer configured to receive a second output from the first line buffer, a third line buffer configured to receive a third output from the second line buffer, a fourth line buffer configured to receive a fourth output from the third line buffer, and a fifth line buffer configured to receive a fifth output from the fourth line buffer;
• and
• wherein the second subset of line buffers comprises a sixth line buffer configured to receive a sixth output from the fifth line buffer, a seventh line buffer configured to receive a seventh output from the sixth line buffer, an eighth line buffer configured to receive an eighth output from the seventh line buffer, a ninth line buffer configured to receive a ninth output from the eighth line buffer, and a tenth line buffer configured to receive a tenth output from the ninth line buffer.

A method for implementing a raw processing pipeline of an image signal processing system comprising:

• providing a first line of logic configured to receive raw image pixels acquire using an image sensor, wherein the first line of logic is used to implement a first gain, offset, and clamping logic, a first portion of defective pixel correction logic, and a first portion of green non-uniformity (GNU) correction logic;
• providing an arrangement of line buffers comprising a first subset of line buffers and a second subset of line buffers, wherein the first subset of line buffers comprises a first line buffer, a second line buffer, a third line buffer, a fourth line buffer, and a fifth line buffer, and wherein the second subset of logic comprises a sixth line buffer, a seventh line buffer, an eighth line buffer, a ninth line buffer, and a tenth line buffer, wherein the first subset of line buffers is used to implement a second portion of the defective pixel correction logic, a second portion of the GNU correction logic, a horizontal noise reduction filter, and a first portion of a vertical noise reduction filter and wherein the second subset of line buffers is used to implement a second portion of the vertical noise reduction filter, lens shading correction logic, a second gain, offset, and clamping logic, and demosaicing logic;
• and
• communicatively coupling an output of the first line of logic to an input of the first line buffer, an output of the first line buffer to an input of the second line buffer, an output of the second line buffer to an input of the third line buffer, an output of the third line buffer to an input of the fourth line buffer, an output of the fourth line buffer to an input of the fifth line buffer, an output of the fifth line buffer to an input of the sixth line buffer, an output of the sixth line buffer to an input of the seventh line buffer, an output of the seventh line buffer to an input of the eighth line buffer, an output of the eighth line buffer to an input of the ninth line buffer, and an output of the ninth line buffer to an input of the tenth line buffer;
• wherein the raw pixel processing pipeline is configured to process the raw image pixels to produce corresponding RGB image pixels.

An electronic device comprising:

• an image sensor configured to acquire raw image data comprising a plurality of raw pixels representative of an image scene;
• an image signal processing sub-system;
• and
• a sensor interface configured to provide the raw pixels from the image sensor to the image signal processing sub-system, wherein the image signal processing sub-system comprises an image pixel processing pipeline having a raw pixel processing unit comprising:
• a first gain, offset, and clamping logic implemented using a first row of logic;
• a first subset of line buffers comprising a first line buffer, a second line buffer, a third line buffer, a fourth line buffer, and a fifth line buffer;
• a second subset of line buffers comprising a sixth line buffer, a seventh line buffer, an eighth line buffer, a ninth line buffer, and a tenth line buffer;
• defective pixel correction and detection unit implemented using the first row of logic and at least a portion of the first subset of line buffers;
• noise reduction logic implemented using the first row of logic, the first subset of line buffers, and the second subset of line buffers;
• lens shading correction logic implemented using the second subset of line buffers;
• a second gain, offset, and clamping logic implemented using the second subset of line buffers;
• and
• demosaicing logic implemented using the second subset of line buffers, wherein the demosaicing logic is configured to convert the raw pixels into RGB pixels, wherein an output of the first row of logic is provided to an input of the first line buffer, wherein an output of the first line buffer is provided to an input of the second line buffer, wherein an output of the second line buffer is provided to an input of the third line buffer, wherein an output of the third line buffer is provided to an input of the fourth line buffer, wherein an output of the fourth line buffer is provided to an input of the fifth line buffer, wherein an output of the fifth line buffer is provided to an input of the sixth line buffer, wherein an output of the sixth line buffer is provided to an input of the seventh line buffer, wherein an output of the seventh line buffer is provided to an input of the eighth line buffer, wherein an output of the eighth line buffer is provided to an input of the ninth line buffer, wherein an output of the ninth line buffer is provided to an input of the tenth line buffer.

An electronic device comprising:

• an image sensor configured to acquire raw image data comprising a plurality of raw pixels representative of an image scene;
• an image signal processing sub-system;
• and
• a sensor interface configured to provide the raw pixels from the image sensor to the image signal processing sub-system, wherein the image signal processing sub-system comprises an image pixel processing pipeline having a raw pixel processing unit comprising:
• a first gain, offset, and clamping logic implemented using a first row of logic;
• a first subset of line buffers comprising a first line buffer, a second line buffer, a third line buffer, a fourth line buffer, and a fifth line buffer;
• a second subset of line buffers comprising a sixth line buffer, a seventh line buffer, an eighth line buffer, a ninth line buffer, and a tenth line buffer;
• defective pixel correction and detection unit implemented using the first row of logic and at least a portion of the first subset of line buffers;
• noise reduction logic implemented using the first row of logic, the first subset of line buffers, and the second subset of line buffers;
• lens shading correction logic implemented using the second subset of line buffers;
• a second gain, offset, and clamping logic implemented using the second subset of line buffers;
• and
• demosaicing logic implemented using the second subset of line buffers, wherein the noise reduction logic comprises:
• a horizontal filter implemented using at least one line buffer from the first subset of line buffers;
• and
• a vertical filter implemented using the second set of line buffers and at least a portion of the first subset of line buffers.

An electronic device comprising:

• an image sensor configured to acquire raw image data comprising a plurality of raw pixels representative of an image scene;
• an image signal processing sub-system;
• and
• a sensor interface configured to provide the raw pixels from the image sensor to the image signal processing sub-system, wherein the image signal processing sub-system comprises an image pixel processing pipeline having a raw pixel processing unit comprising:
• a first gain, offset, and clamping logic implemented using a first row of logic;
• a first subset of line buffers comprising a first line buffer, a second line buffer, a third line buffer, a fourth line buffer, and a fifth line buffer;
• a second subset of line buffers comprising a sixth line buffer, a seventh line buffer, an eighth line buffer, a ninth line buffer, and a tenth line buffer;
• defective pixel correction and detection unit implemented using the first row of logic and at least a portion of the first subset of line buffers;
• noise reduction logic implemented using the first row of logic, the first subset of line buffers, and the second subset of line buffers;
• lens shading correction logic implemented using the second subset of line buffers;
• a second gain, offset, and clamping logic implemented using the second subset of line buffers;
• and
• demosaicing logic implemented using the second subset of line buffers, comprising a control register, wherein the vertical filter is configured to operate in a recursive mode if the control register indicates a first state and in a non-recursive mode if the control register indicates a second state.