Plasma display device
AssigneePanasonic Corporation
InventorKazuki Sawa
Life of this patent
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Abstract
A plasma display device includes an image signal processing circuit having a sequential addressing processing circuit, an alternate addressing processing circuit and an image data selection circuit. The sequential addressing processing circuit includes a sequential addressing array unit for converting an image signal into image data arranged in the order corresponding to a sequential address operation. The alternate addressing processing circuit includes an alternate addressing array unit for converting an image signal into image data arranged in the order corresponding to an alternate address operation. The image data selecting circuit selecting between the sequential and alternate addressing operations based on predicted power consumption.
Claims6
A plasma display device comprising:
- a sequential addressing processing circuit including:
- a sequential addressing array unit for arranging a received image data into sequential image data corresponding to a sequential address operation for sequentially driving scan electrodes in the plasma display device,
- a sequential data power conversion unit for converting gradation values in the sequential image data to reduce power consumption when sequentially driving the scan electrodes, and
- a sequential power prediction unit for predicting the power consumption when sequentially driving the scan electrodes;
- an alternate addressing processing circuit including:
- an alternate addressing array unit for arranging the received image data into alternate image data corresponding to an alternate address operation for alternately driving the scan electrodes in the plasma display device,
- an alternate data power conversion unit for converting gradation values in the alternate image data to reduce power consumption when alternately driving the scan electrodes, and
- an alternate power prediction unit for predicting the power consumption when alternately driving the scan electrodes;
- and
- an image data selection circuit for selecting between an output of the sequential addressing processing circuit and an output of the alternate addressing processing circuit based on the predicted power consumption when sequentially driving the scan electrodes, and the predicted power consumption when alternately driving the scan electrodes.
Dependencies are inferred from the claim text.