Scanning signal line drive circuit and display device including the same

A driving method for driving a plurality of scanning signal lines arrayed in a display unit, by a scanning signal line drive circuit including m shift registers, each of the m shift registers including a plurality of bistable circuits having a first state and a second state and connected in series with each other, and each of the m shift registers operating based on a plurality of clock signals that cyclically repeat a first level change of changing from a second level to a first level and a second level change of changing from the first level to the second level, and in each of the m shift registers, the plurality of bistable circuits sequentially become in the first state by one of the plurality of clock signals being provided to each bistable circuit as a scanning signal line drive clock signal, the method comprising:

• a first drive step for changing each bistable circuit from the second state to the first state;
• and
• a second drive step for changing each bistable circuit from the first state to the second state, wherein
• the plurality of clock signals provided to the m shift registers as the scanning signal line drive clock signals, each of the scanning signal line drive clock signals having a specific phase at which a change between the first level change and the second level change occurs, the specific phase being different for the scanning signal line drive clock signals of different ones of the m shift registers,
• each bistable circuit includes:
• an output node that is connected to the scanning signal line and that outputs a state signal which indicates either one of the first state as an on level and the second state as an off level,
• an output control switching element having a second electrode to which the scanning signal line drive clock signal is provided and a third electrode connected to the output node, and
• a first node connected to a first electrode of the output control switching element, and
• in each bistable circuit,
• the first drive step includes
• a first node turn-on step of changing a level of the first node to an on level based on the state signal which is outputted from a bistable circuit of a previous stage of the bistable circuit concerned, and
• a state signal turn-on step of changing a level of the state signal to an on level based on the first level change of the scanning signal line drive clock signal,
• the second drive step includes
• a state signal turn-off step of changing a level of the state signal to an off level based on the second level change of the scanning signal line drive clock signal, and
• a first node turn-off step of receiving the state signal which is outputted from a bistable circuit of a subsequent stage of the bistable circuit concerned, as a first node turn-off signal, and changing a level of the first node to an off level based on the first node turn-off signal,
• after the state signal turn-on step ends, and after the state signal turn-off step is started, the first node turn-off step is started, during a period from a time point after a bistable circuit of a next stage of the bistable circuit concerned in a shift register of the m shift registers that includes the bistable circuit concerned completes the state signal turn-on step till a time point when the scanning signal line drive clock signal performs the first level change,
• the m shift registers sequentially output the state signal in the first state for each one of the plurality of scanning signal lines,
• the first node turn-off signal for each respective bistable circuit in an entire shift register array including the m shift registers is the state signal that is outputted from a bistable circuit of a k-th stage after the bistable circuit concerned, and
• a relationship between m and k satisfies the following equation:
• m+1≦k≦2m−1,
• where m is an integer equal to or larger than two.