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US 8,508,459 B2Granted
Pulse output circuit, shift register, and display device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHiroyuki Miyake
Life of this patent
Estimating the term…
Abstract
An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.
Claims17
A semiconductor device comprising:
- a pulse output circuit over a substrate, comprising:
- first to ninth transistors;
- first to sixth input terminals;
- and
- an output terminal,
- wherein the pulse output circuit is electrically connected to first to fifth power supply lines,
- wherein a first electrode of the first transistor is electrically connected to the first power supply line, a second electrode of the first transistor is electrically connected to a gate electrode of the third transistor, and a gate electrode of the first transistor is electrically connected to the fourth input terminal,
- wherein a first electrode of the second transistor is electrically connected to the second power supply line, a second electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and a gate electrode of the second transistor is electrically connected to a gate electrode of the fourth transistor,
- wherein a first electrode of the third transistor is electrically connected to the first input terminal and a second electrode of the third transistor is electrically connected to the output terminal,
- wherein a first electrode of the fourth transistor is electrically connected to the third power supply line and a second electrode of the fourth transistor is electrically connected to the output terminal,
- wherein a first electrode of the fifth transistor is electrically connected to the fourth power supply line, a second electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the fifth transistor is electrically connected to the fourth input terminal,
- wherein a first electrode of the sixth transistor is electrically connected to the fourth power supply line, a second electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the sixth transistor is electrically connected to the fifth input terminal,
- wherein a first electrode of the seventh transistor is electrically connected to the fifth power supply line, a second electrode of the seventh transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the seventh transistor is electrically connected to the sixth input terminal,
- wherein a first electrode of the eighth transistor is electrically connected to the fifth power supply line, a second electrode of the eighth transistor is electrically connected to a second electrode of the ninth transistor, and a gate electrode of the eighth transistor is electrically connected to the second input terminal, and
- wherein a first electrode of the ninth transistor is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a gate electrode of the ninth transistor is electrically connected to the third input terminal.
12 more elements
A semiconductor device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- a fourth transistor;
- a fifth transistor;
- a sixth transistor;
- a seventh transistor;
- an eighth transistor;
- and
- a ninth transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the third transistor,
- wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
- wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,
- wherein a gate of the fifth transistor is electrically connected to a gate of the first transistor,
- wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,
- wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
- wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
- wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
- wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the seventh transistor,
- wherein the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor, and
- wherein the other of the source and the drain of the ninth transistor is electrically connected to the gate of the second transistor.
19 more elements
A display device comprising:
- a pixel portion over a substrate;
- and
- a driver circuit over the substrate, the driver circuit comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- a fourth transistor;
- a fifth transistor;
- a sixth transistor;
- a seventh transistor;
- an eighth transistor;
- and
- a ninth transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the third transistor,
- wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
- wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,
- wherein a gate of the fifth transistor is electrically connected to a gate of the first transistor,
- wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,
- wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
- wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
- wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
- wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the seventh transistor,
- wherein the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor, and
- wherein the other of the source and the drain of the ninth transistor is electrically connected to the gate of the second transistor.
22 more elements
Dependencies are inferred from the claim text.