US 8,508,400 B2Granted

Successive approximation register analog to digital converter and conversion method thereof

AssigneeMediatek Inc.

InventorsMeng Hsuan Wu, Yung-Hui Chung

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Abstract

A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

Claims17

Dependent claims

A successive approximation register (SAR) analog to digital converter (ADC) for converting an analog input signal into a digital output signal, comprising:

a digital to analog converter, having an input terminal for receiving the analog input signal and an output terminal for providing an intermediate analog signal according to the analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance, and comprising:
a first switched capacitor array coupled to the input and output terminals of the digital to analog converter, selectively providing the most significant bit capacitance or the significant bit capacitances according to a select signal, wherein the sum of the significant bit capacitances is equal to the most significant bit capacitance;
and
a second switched capacitor array coupled to the input and output terminals of the digital to analog converter, providing the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and providing the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances;
a comparator, providing a comparison result according to the intermediate analog signal;
and
a SAR logic, providing the digital output signal according to the comparison result.

4 more elements

A conversion method for a successive approximation register (SAR) analog to digital converter (ADC) having a digital to analog converter and a SAR logic, comprising:

selectively providing a most significant bit capacitance or a plurality of significant bit capacitances smaller than the most significant bit capacitance according to a select signal by a first switched capacitor array of the digital to analog converter;
providing the most significant bit capacitance by a second switched capacitor array of the digital to analog converter when the significant bit capacitances are provided by the first switched capacitor array;
providing the significant bit capacitances by the second switched capacitor array when the most significant bit capacitance is provided by the first switched capacitor array;
obtaining an intermediate analog signal according to an analog input signal, the most significant bit capacitance and the significant bit capacitances;
providing a comparison result according to the intermediate analog signal;
and
providing a digital output signal according to the comparison result by the SAR logic.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/479,021Filed 23 May 2012 · us provisional application
Priority: 24 Jun 2011
Published: US 2012/0326900 A127 Dec 2012
Granted: 13 Aug 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H03M 1/0673
By continuously permuting the elements used, i.e. dynamic element matching: using random selection of the elements
H03M 1/468
Using switched capacitors: in which the input S/H circuit is merged with the feedback DAC array
H03M
Coding