Successive approximation analog to digital converter and method of analog to digital conversion
AssigneeSamsung Electronics Co., Ltd.
InventorsJung-Ho Lee, Sung-Sang Lim, Yong-Woo Kim, Michael Choi
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Abstract
An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.
Claims18
An analog to digital converter, comprising:
- a digital to analog converting circuit configured to sample and hold an analog input signal, and convert digital output data to an analog signal to generate a hold voltage signal;
- a comparator configured to compare the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal;
- and
- a signal processing circuit configured to perform successive approximation based on the comparison output voltage signal to generate the digital output data,
- wherein the signal processing circuit comprises:
- a demultiplexer configured to perform demultiplexing on the comparison output voltage signal in response to a selecting signal;
- and
- a plurality of SR latches configured to latch and output one of a plurality of output signals of the demultiplexer in response to each bit of a conversion control signal.
An analog to digital converter, comprising:
- a digital to analog converting circuit configured to sample and hold an analog input signal, and convert digital output data to an analog signal to generate a hold voltage signal;
- a preamplifier configured to amplify a difference between the hold voltage signal and a reference voltage signal;
- a comparator configured to compare differential output voltage signals of the preamplifier with each other in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal;
- and
- a signal processing circuit configured to perform successive approximation based on the comparison output voltage signal to generate the digital output data,
- wherein the signal processing circuit comprises:
- a demultiplexer configured to perform demultiplexing on the comparison output voltage signal in response to a selecting signal;
- and
- plurality of SR latches configured to latch and output one of a plurality of output signals of the demultiplexer in response to each bit of a conversion control signal.
An analog to digital converter, comprising:
- a digital to analog converting circuit configured to generate a hold voltage signal based on an analog input signal and digital output data;
- a first comparator configured to compare the hold voltage signal with a reference voltage signal in response to a first clock signal to generate a first comparison output voltage signal;
- a second comparator configured to compare the hold voltage signal with the reference voltage in response to a second clock signal opposite in phase to the first clock signal to generate a second comparison signal;
- and
- a signal processing circuit configured to perform successive approximation based on a comparison output voltage signal output by the comparator to generate the digital output data,
- wherein the comparison output voltage signal is based on both the first and second comparison output voltage signals,
- wherein the signal processing circuit comprises:
- a demultiplexer configured to perform demultiplexing on the comparison output voltage signal in response to a selecting signal to generate a plurality of demultiplexed signals;
- and
- a plurality of SR latches configured to latch a corresponding one of the demultiplexed signals in response to a conversion control signal, wherein each SR latch receives a corresponding one bit of the conversion control signal.
Dependencies are inferred from the claim text.