Systems for comparator offset cancellation in successive-approximation-register analog-to-digital converters

A system for a successive-approximation-register analog-to-digital-converter (SAR ADC), the system comprising:

• a first capacitive digital-to-analog converter (DAC), the first capacitive DAC having a size less than a second DAC of the SAR ADC, each of the first and second capacitive DACs receiving a value and a reference value;
• a first conversion control module that generates first and second signals for a comparator of the SAR ADC based on outputs of the first and second capacitive DACs and an analog input signal;
• a second conversion control module that generates third and fourth signals for an SAR control module of the SAR ADC based on outputs of the comparator;
• and
• the SAR control module, the SAR control module configured to (i) control the first and second conversion control modules during a full conversion and a partial conversion, the full conversion preceding the partial conversion, (ii) determine an offset of the comparator based on the third and fourth signals received from the second conversion control module during each of the full and partial conversions, and (iii) control the SAR ADC based on the determined comparator offset,
• wherein a least significant bit (LSB) of the first capacitive DAC is aligned to an LSB of the second capacitive DAC.

A successive-approximation-register analog-to-digital converter (SAR ADC), comprising:

• an N-bit capacitive digital-to-analog converter (DAC) that generates first and second analog signals based on an input value and a reference value;
• an M-bit capacitive DAC that generates third and fourth analog signals based on the same input value and the reference value;
• a first conversion control system that generates first and second comparator signals based on the first, second, third, and fourth analog signals, and an analog input signal;
• a comparator that generates first and second comparison signals based on the first and second comparator signals;
• a second conversion control system that generates first and second conversion signals based on the first and second comparator signals;
• and
• an SAR control module that (i) receives the first and second conversion signals, (ii) controls the first and second conversion control systems during both a full N-bit conversion and a following partial M-bit conversion to determine an offset of the comparator based on the first and second conversion signals received during each of the full N-bit conversion and the partial M-bit conversion, and (iii) controls future conversions of the SAR ADC based on the determined comparator offset.