High-frequency power amplifier

A high-frequency power amplifier comprising:

• a first terminal where a first power signal is input;
• a second terminal where a second power signal is output, the second power signal being generated by amplifying the first power signal;
• a first power amplification transistor;
• a second power amplification transistor sized smaller than the first power amplification transistor;
• a third power amplification transistor sized smaller than the second power amplification transistor;
• a first output impedance matching circuit provided between an output node for the first power amplification transistor and a first node;
• a second output impedance matching circuit provided between an output node for the second power amplification transistor and the first node;
• a third output impedance matching circuit provided between an output node for the third power amplification transistor and the first node;
• a common output impedance matching circuit provided between the first node and the second terminal;
• a fourth power amplification transistor provided prior to the first and the second power amplification transistors in common;
• a first interstage impedance matching circuit provided between an output node for the fourth power amplification transistor and an input node for the first power amplification transistor;
• a second interstage impedance matching circuit provided between an output node for the fourth power amplification transistor and an input node for the second power amplification transistor;
• a fifth power amplification transistor that is provided prior to the third power amplification transistor and is sized smaller than the fourth power amplification transistor;
• a third interstage impedance matching circuit provided between an output node for the fifth power amplification transistor and an input node for the third power amplification transistor;
• a common input impedance matching circuit provided between the first terminal and the second node;
• a first input impedance matching circuit provided between the second node and an input node for the fourth power amplification transistor;
• a second input impedance matching circuit provided between the second node and an input node for the fifth power amplification transistor;
• and
• a control circuit that provides control to activate one of the first through the third power amplification transistors and one of the fourth and the fifth power amplification transistors and inactivate the remaining power amplification transistors in accordance with a power specification signal for configuring a power level of the second power signal.

A high-frequency power amplifier comprising:

• a first terminal where a first power signal is input;
• a second terminal where a second power signal is output, the second power signal being generated by amplifying the first power signal;
• a first power amplification transistor;
• a second power amplification transistor sized smaller than the first power amplification transistor;
• a first output impedance matching circuit provided between an output node for the first power amplification transistor and a first node;
• a second output impedance matching circuit provided between an output node for the second power amplification transistor and the first node;
• a common output impedance matching circuit provided between the first node and the second terminal;
• a third power amplification transistor provided prior to the first power amplification transistor;
• a first interstage impedance matching circuit provided between an output node for the third power amplification transistor and an input node for the first power amplification transistor;
• a fourth power amplification transistor that is provided prior to the second power amplification transistor and is sized smaller than the third power amplification transistor;
• a second interstage impedance matching circuit provided between an output node for the fourth power amplification transistor and an input node for the second power amplification transistor;
• a common input impedance matching circuit provided between the first terminal and the second node;
• a first input impedance matching circuit provided between the second node and an input node for the third power amplification transistor;
• a second input impedance matching circuit provided between the second node and an input node for the fourth power amplification transistor;
• a control circuit that provides control to put the first through the fourth power amplification transistors into one of active state and inactive state in accordance with a power specification signal for configuring a power level of the second power signal,
• wherein the first power amplification transistor is configured by coupling in parallel a first-A power amplification transistor and a first-B power amplification transistor,
• wherein the third power amplification transistor is configured by coupling in parallel a third-A power amplification transistor and a third-B power amplification transistor,
• wherein the control circuit, in accordance with the power specification signal, provides control to put the first-A, the first-B, and the second power amplification transistors into one of sets of “active state, active state, and inactive state,” “active state, inactive state, and inactive state,” and “inactive state, inactive state, and active state,” respectively, and to put the third-A, the third-B, and the fourth power amplification transistors into one of sets of “active state, active state, and inactive state,” “active state, inactive state, and inactive state,” and “inactive state, inactive state, and active state,” respectively.