Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
AssigneeSoitec
InventorsCarlos Mazure, Richard Ferrant
Life of this patent
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AssigneeSoitec
InventorsCarlos Mazure, Richard Ferrant
Estimating the term…
This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.
A data-path cell fabricated on a semiconductor-on-insulator substrate comprising a surface layer of semiconductor material separated from a bulk substrate by a buried insulating layer, the cell comprising:
A data-path cell fabricated on a semiconductor-on-insulator substrate comprising a surface layer of semiconductor material separated from a bulk substrate by a buried insulating layer, the cell comprising:
Dependencies are inferred from the claim text.