US 8,508,286 B2Granted

Apparatus and method for electrical biasing

AssigneeAnalog Devices, Inc.

InventorsJennifer Lloyd, Kimo Tam

Life of this patent

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Abstract

As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.

Claims18

Dependent claims

An apparatus comprising:

an active circuit including a first bias node;
a replica circuit configured to contribute to the biasing of the active circuit, wherein the replica circuit includes a second bias node and an output configured to generate a first electrical output, wherein the replica circuit is a replica of at least a portion of the active circuit;
an error detection circuit configured to generate an error signal based at least partly on a comparison between an electrical reference and the first electrical output of the replica circuit;
a first controllable electrical source operatively coupled between the error detection circuit and the replica circuit, wherein the first controllable electrical source is configured to control a bias condition of the second bias node based on the error signal;
and
a second controllable electrical source operatively coupled between the error detection circuit and the active circuit, wherein the second controllable electrical source is configured to control a bias condition of the first bias node based on the error signal,
wherein the active circuit further includes an input configured to receive a data signal, and wherein the replica circuit further includes an input configured to receive the data signal.

4 more elements

An apparatus comprising:

an active circuit including a first bias node;
a replica circuit configured to contribute to the biasing of the active circuit, wherein the replica circuit includes a second bias node and an output configured to generate a first electrical output, wherein the replica circuit is a replica of at least a portion of the active circuit;
an error detection circuit configured to generate an error signal based at least partly on a comparison between an electrical reference and the first electrical output of the replica circuit;
a first controllable electrical source operatively coupled between the error detection circuit and the replica circuit, wherein the first controllable electrical source is configured to control a bias condition of the second bias node based on the error signal;
and
a second controllable electrical source operatively coupled between the error detection circuit and the active circuit, wherein the second controllable electrical source is configured to control a bias condition of the first bias node based on the error signal,
wherein the error signal is a voltage signal,
wherein the first controllable electrical source includes a first voltage controlled current source configured to receive the voltage signal and to generate a first current, and wherein the second controllable electrical source includes a second voltage controlled current source configured to receive the voltage signal and to generate a second current, and wherein the first controllable electrical source is configured to control the bias condition of the second bias node based on the first current, and wherein the second controllable electrical source is configured to control the bias condition of the first bias node based on the second current, and
wherein the second controllable electrical source further includes a first plurality of current controlled current sources configured to receive the second current, wherein at least a portion of the first plurality of current controlled current sources can be selectively switched between an activated and a deactivated state.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/586,544Filed 15 Aug 2012 · continuation
Priority: 24 Aug 2010
Published: US 2013/0043937 A121 Feb 2013
Granted: 13 Aug 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03F 1/30
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements: modifications of…
H03F 1/0283
In transistor amplifiers: reducing the number of DC-current paths
H03K 19/0008
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: arrangements for reducing power consumption
H03F 2200/18
Indexing scheme relating to amplifiers: the bias of the gate of a FET being controlled by a control signal

Family

Application12/862,171Parent of this continuation · filed 24 Aug 2010
US 2013/0043937 A1Pre-grant publication · published 21 Feb 2013
US 8,248,151 B2Parent of this continuation
US 2012/0049941 A1Published application
US 8,508,286 B2This patent

From the US filing history. Foreign family members aren’t listed.