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US 8,508,278 B2Granted
Apparatus and method for external to internal clock generation
AssigneeMicron Technology, Inc.
InventorsMichael V. Ho, Tyler J. Gomm, Scott E. Smith
Life of this patent
Estimating the term…
Abstract
A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.
Claims15
A method comprising:
- inputting a first transition associated with a first clock signal to a first buffer;
- generating a first pulse at a single output from the first buffer to latch an output signal at a circuit output to a first state;
- inputting a second transition associated with a second clock signal to a second buffer;
- generating a second pulse at a single output from the second buffer to latch the output signal at the circuit output to a second state, wherein the output signal and one of the first and second clock signals have the same phase;
- providing a signal from the first buffer to a first multiplexor;
- providing a signal from the second buffer to a second multiplexor;
- and
- coupling an output of the first multiplexor and an output of the second multiplexor to the circuit output, such that output signal of the circuit output is latched to the first state in response to the first pulse and to the second state in response to the second pulse.
5 more elements
A method comprising:
- triggering a first signal at a single output of a first pulse generator;
- triggering a second signal at a single output second pulse generator;
- combining signals generated based on the first signal at the single output from the first pulse generator and the second signal at the single output from the second pulse generator to produce a clock signal at a circuit output;
- causing the clock signal to make a transition from a first signal level to a second signal level in response to the first signal;
- causing the clock signal to make a transition from the second signal level to the first signal level in response to the second signal;
- providing a signal from the first pulse generator to a first multiplexor;
- providing a signal from the second pulse generator to a second multiplexor;
- coupling an output of the first multiplexor and an output of the second multiplexor to the circuit output to cause the clock signal to make the transition from the first signal level to the second signal and to cause the clock signal to make the transition from the second signal level to the first signal level;
- inputting a first clock signal to a buffer;
- using a signal at output of the first buffer to trigger the first signal;
- inputting a second clock signal to a second buffer;
- and
- using a signal at output of the second buffer to trigger the second signal, wherein the clock signal and one of the first and second clock signals have the same phase.
10 more elements
Dependencies are inferred from the claim text.