Phase interpolator, reception circuit and information processing apparatus

A reception circuit comprising:

• a periodic signal generation circuit that generates a first periodic signal and a second periodic signal that has a phase different from that of the first periodic signal;
• a first signal generation circuit that generates a first output signal that has a phase corresponding to the phase of the first periodic signal that has been input;
• a second signal generation circuit that generates a second output signal that has a phase corresponding to the phase of the second periodic signal that has been input;
• a third signal generation circuit that generates a third periodic signal by synthesizing the first output signal and the second output signal;
• a delay circuit that delays the first periodic signal;
• a detection circuit that detects a value of the third periodic signal at a timing corresponding to the phase of the first periodic signal that is delayed by the delay circuit;
• an optimum delay amount obtaining circuit that compares the value of the third periodic signal detected by the detection circuit according to the first periodic signal that has the delay amount with the value of the third periodic signal detected by the detection circuit according to the first periodic signal that has the different delay amount and obtains as an optimum delay amount the delay amount at which it is determined that the detected value of the third periodic signal is a maximum or a minimum;
• an amplitude adjustment circuit that adjusts an amplitude of the third periodic signal in such a manner that the value of the third periodic signal detected by the detection circuit at the optimum delay amount falls within a predetermined range;
• a data taking circuit that takes reception data from a reception signal at a timing corresponding to a phase of the third periodic signal;
• and
• a phase adjuster that adjusts the phase of the third periodic signal by adjusting an amplitude of the first output signal and an amplitude of the second output signal.

An information processing apparatus comprising:

• an arithmetic and logic unit;
• a storage unit that stores data to be used by the arithmetic and logic unit for operations and stores data obtained from the operations;
• and
• a control unit that controls operations of the arithmetic and logic unit and the storage unit, wherein
• at least one of the arithmetic and logic unit, the storage unit and the control unit includes a reception circuit that receives data from another unit, and
• the reception circuit includes
• a periodic signal generation circuit that generates a first periodic signal and a second periodic signal that has a phase different from that of the first periodic signal,
• a first signal generation circuit that generates a first output signal that has a phase corresponding to the phase of the first periodic signal that has been input,
• a second signal generation circuit that generates a second output signal that has a phase corresponding to the phase of the second periodic signal that has been input,
• a third signal generation circuit that generates a third periodic signal by synthesizing the first output signal and the second output signal,
• a delay circuit that delays the first periodic signal,
• a detection circuit that detects a value of the third periodic signal at a timing corresponding to the phase of the first periodic signal that is delayed by the delay circuit,
• an optimum delay amount obtaining circuit that compares the value of the third periodic signal detected by the detection circuit according to the first periodic signal that has the delay amount with the value of the third periodic signal detected by the detection circuit according to the first periodic signal that has the different delay amount and obtains as an optimum delay amount the delay amount at which it is determined that the detected value of the third periodic signal is a maximum or a minimum,
• an amplitude adjustment circuit that adjusts an amplitude of the third periodic signal in such a manner that the value of the third periodic signal detected by the detection circuit at the optimum delay amount falls within a predetermined range,
• a data taking circuit that takes reception data from a reception signal at a timing corresponding to a phase of the third periodic signal, and
• a phase adjuster that adjusts the phase of the third periodic signal by adjusting an amplitude of the first output signal and an amplitude of the second output signal.