Semiconductor device including latch circuit
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorTakehisa Hatano
Life of this patent
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Abstract
The latch circuit includes a transistor whose channel region is formed with an oxide semiconductor (OS). Data is held in a node that is electrically connected to an output terminal and one of a source and a drain of the transistor and brought into a floating state when the transistor is turned off. Note that the oxide semiconductor has a band gap wider than silicon and an intrinsic carrier density lower than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized.
Claims23
A semiconductor device comprising a latch circuit, the latch circuit comprising a first inverter, a second inverter, a first transistor, a second transistor, and a node, wherein a gate of the first transistor is electrically connected to an output terminal of the first inverter,
- wherein one of a source and a drain of the first transistor is electrically connected to the node,
- wherein the other of the source and the drain of the first transistor is electrically connected to an input terminal of the second inverter,
- wherein a gate of the second transistor is electrically connected to an output terminal of the second inverter,
- wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first inverter,
- wherein the other of the source and the drain of the second transistor is electrically connected to the node, and
- wherein an oxide semiconductor is included in a channel region in each of the first transistor and the second transistor.
A semiconductor device comprising a latch circuit, the latch circuit comprising a first inverter, a second inverter, a first transistor, a second transistor, and a node,
- wherein a gate of the first transistor is electrically connected to an output terminal of the first inverter,
- wherein one of a source and a drain of the first transistor is electrically connected to the node,
- wherein the other of the source and the drain of the first transistor is electrically connected to an input terminal of the second inverter,
- wherein a gate of the second transistor is electrically connected to an output terminal of the second inverter,
- wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first inverter,
- wherein the other of the source and the drain of the second transistor is electrically connected to the node,
- wherein an oxide semiconductor is included in a channel region in each of the first transistor and the second transistor,
- wherein the first inverter includes a transistor, and
- wherein the first transistor and the second transistor are located over the transistor.
A semiconductor device comprising a latch circuit, the latch circuit comprising a first inverter, a second inverter, a first transistor, a second transistor, and a node,
- wherein a gate of the first transistor is electrically connected to an output terminal of the first inverter,
- wherein one of a source and a drain of the first transistor is electrically connected to the node,
- wherein the other of the source and the drain of the first transistor is electrically connected to an input terminal of the second inverter,
- wherein a gate of the second transistor is electrically connected to an output terminal of the second inverter,
- wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first inverter,
- wherein the other of the source and the drain of the second transistor is electrically connected to the node,
- wherein an oxide semiconductor is included in a channel region in each of the first transistor and the second transistor,
- wherein the first inverter includes a transistor whose channel formation region is included in a semiconductor substrate, and
- wherein the first transistor and the second transistor are located over the transistor.
Dependencies are inferred from the claim text.