Differential controlled phase locked loop circuit
AssigneeElectronics and Telecommunications Research Institute
InventorSeok Ju Yun
Life of this patent
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Abstract
Provided is a PLL circuit driven with a differential controlled voltage. The PLL circuit includes a VCO. The VCO outputs an oscillation signal in response to a difference between first and second control voltages. The PLL circuit includes a first loop for generating the first control voltage, and a second loop for generating the second control voltage having a phase opposite to the first control voltage. Intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases.
Claims7
A phase locked loop (PLL) circuit, comprising:
- a first phase frequency detector configured to output a first differential control signal in response to a reference signal and a division signal for an oscillation signal;
- a second phase frequency detector configured to output a second differential control signal in response to an inverted reference signal and an inverted division signal;
- a first charge pump configured to output a first current that is controlled according to the first differential control signal;
- a second charge pump configured to output a second current that is controlled according to the second differential control signal;
- a first loop filter configured to output a first control voltage that corresponds to the first current;
- a second loop filter configured to output a second control voltage that corresponds to the second current;
- a voltage controlled oscillator (VCO) configured to output the oscillation signal in response to a difference between the first and second control voltages;
- a first switch configured to selectively couple the first charge pump and the first loop filter in response to a first switch control signal;
- and
- a second switch configured to selectively couple the second charge pump and the second loop filter in response to a second switch control signal.
A Phase Locked Loop (PLL) circuit comprising:
- a first phase frequency detector configured to output a first differential control signal in response to a reference signal and a division signal for an oscillation signal;
- a second phase frequency detector configured to output a second differential control signal in response to an inverted reference signal and an inverted division signal;
- first to third charge pumps configured to output first to third currents that are controlled according to the first differential control signal, respectively;
- a fourth charge pump configured to output a fourth current that is controlled according to the second differential control signal;
- a first loop filter configured to output a first control voltage that corresponds to a sum of the first and second currents;
- a second loop filter configured to output a second control voltage that corresponds to a sum of the third and fourth currents;
- and
- a Voltage Controlled Oscillator (VCO) configured to output the oscillation signal in response to a difference between the first and second control voltages.
Dependencies are inferred from the claim text.