Power on reset apparatus
AssigneeTexas Instruments Incorporated
InventorsBinan C. Wang, Paul Stulik
Life of this patent
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Abstract
A power on reset (POR) circuit is provided. For the POR circuit, a PMOS transistor is coupled to a first voltage rail at its source. A drive circuit is coupled to the drain of the PMOS transistor and is configured to output a POR signal. A voltage divider is coupled between the drain of the PMOS transistor and the second voltage rail. A switch network is provided as well, which has first and second switches. The first switch is coupled between the gate of the PMOS transistor and the voltage divider, and the second switch is coupled between the gate of the PMOS transistor and the voltage divider. A controller is also coupled to control the first and second switches, wherein the first and second switches are complementary driven.
Claims5
An apparatus comprising:
- a first voltage rail;
- a second voltage rail;
- a PMOS transistor that is coupled to the first voltage rail at its source;
- an inverter string that is coupled to the drain of the PMOS transistor and that is configured to output a power on reset (POR) signal;
- a voltage divider that is coupled between the drain of the PMOS transistor and the second voltage rail;
- a switch network having:
- a first switch that is coupled between the gate of the PMOS transistor and the voltage divider;
- and
- a second switch that is coupled between the gate of the PMOS transistor and the voltage divider;
- and
- a controller that is coupled to control the first and second switches, wherein the first and second switches are complementary driven;
- wherein the voltage divider further comprises a plurality of impedance elements coupled in series with one another between the drain of the PMOS transistor and the second voltage rail, and wherein the first switch is coupled to a first node within the voltage divider, and wherein the second switch is coupled to a second node within the voltage divider;
- wherein the plurality of impedance elements further comprises a plurality of resistors;
- wherein the first switch further comprises a first NMOS transistor that is coupled to the first node of the voltage divider at its source and the gate of the first PMOS transistor at its drain, and wherein the second switch further comprises a second NMOS transistor that is coupled to the second node of the voltage divider at its source and the gate of the first PMOS transistor at its drain.
Dependencies are inferred from the claim text.