US 8,508,255 B2 · Method and apparatus for reducing power consumption in a digital circuit by controlling the clock

Abstract

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Claims27

Dependent claims

A digital circuit comprising:

a buffer circuit comprising:
a buffer data input;
a buffer data output;
a buffer clock input;
and
a buffer status signal output;
a clocked device coupled to the buffer circuit, the clocked device comprising:
a clocked device data input;
a clocked device data output;
and
a clocked device clock input;
a clock control device comprising:
a clock control device clock input;
a clock control device status signal input;
and
a clock control device clock output;
wherein:
the buffer is configured to transmit a status signal from the buffer status signal output;
the clock control device is configured to:
receive an input clock signal at the clock control device clock input and the status signal at the clock control device status signal input;
generate an output clock signal based on the input clock signal and the status signal;
and
transmit the output clock signal from the clock control device clock output to the clocked device clock input.

20 more elements

Dependencies are inferred from the claim text.

Method and apparatus for reducing power consumption in a digital circuit by controlling the clock

Life of this patent

Method and apparatus for reducing power consumption in a digital circuit by controlling the clock

Life of this patent

Abstract

Claims27