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US 8,508,078 B2Granted
Power switch with reverse current blocking capability
AssigneeDecicon, Inc.
InventorBaris Posat
Life of this patent
Estimating the term…
Abstract
A switching circuit controls the flow of current between its input and output in accordance with the state of a control signal applied to the circuit. When the control signal is in a first state and the voltage applied to the input is higher than the voltage at the output, the circuit provides a low resistance path between its input and output terminals thereby enabling current to flow from the input to the output. When the control signal is in the first state and the voltage at the output is higher than the voltage at the input, the circuit inhibits current flow from the output to the input. When the control signal is in a second state, the circuit is turned off thus inhibiting current flow between the input and the output.
Claims21
A reverse current blocking (RCB) circuit comprising:
- a first transistor having a first current carrying terminal coupled to a first input terminal of the RCB circuit and a second current carrying terminal coupled to a first node;
- a first charge pump operative to supply a first voltage signal to a gate terminal of the first transistor in response to a reference voltage;
- a second transistor having a first current carrying terminal coupled to an output terminal of the RCB circuit, and a second current carrying terminal coupled to the first node;
- a second charge pump operative to supply a second voltage signal to a gate terminal of the second transistor in response to a feedback signal;
- and
- an amplifier having a first input terminal receiving the output voltage of the RCB circuit, and a second input terminal receiving a voltage defined by a voltage of the first node and an offset voltage, said amplifier supplying the feedback signal to the second charge pump.
3 more elements
A circuit comprising:
- a charge pump adapted to supply current to a gate terminal of an MOS transistor;
- a current sense circuit adapted to sense a current flowing through the MOS transistor and to generate a sense signal in response;
- and
- an analog discharge circuit adapted to discharge current from the gate terminal of the MOS transistor, said discharge current being defined by a difference between the sense signal and a reference signal, said discharge current including:
- a first current value associated with a first difference value;
- a second current value larger than the first current value, the second current value being associated with a second difference value larger than the first difference value;
- and
- a third current value larger than the second current value, the third current value being associated with a third difference value larger than the second difference value.
5 more elements
A switching circuit comprising:
- first and second transistors disposed between input and output terminals of the switching circuit;
- a first voltage multiplier generating a first intermediate signal that is a multiple of an analog feedback signal in response to a first phase of a clock signal, said first analog signal having a range defined by first and second supply voltages;
- a second voltage multiplier generating a second intermediate signal that is a multiple of the analog feedback signal in response to a second non-overlapping phase of the clock signal;
- and
- a coupling circuit selectively applying one of the intermediate signals in response to opposite phases of the clock signal to a pair of terminals of at least one of the first and second transistors so as maintain conductive path between the input and output terminals of the switching circuit when the voltage of the input terminal is higher than the voltage of the output terminal, and further to turn off the conduction path between the input and output terminals of the switching circuit when the voltage of the input terminal is smaller than the voltage of the output terminal.
2 more elements
A charge pump circuit comprising:
- two voltage multipliers clocked by opposite phases of a clock signal, each adapted to multiply by a predefined multiplication factor an analog input signal at an analog input terminal changing between a ground and a supply voltage level, the two voltage multipliers each further adapted to alternatingly generate two multiplied analog signals;
- and
- a coupler circuit adapted to selectively couple to an output terminal of the coupler circuit each one of the two multiplied analog signals generated by the two voltage multipliers on opposite phases of the clock signal, thereby maintaining a substantially continuous-time signal path from the analog input terminal to the output terminal of the coupler circuit.
A multiplier circuit comprising:
- a first transistor having a source terminal receiving a feedback voltage, a gate terminal receiving a first non-overlapping pulse signal, and a drain terminal coupled to a first terminal of a first capacitive element, said first transistor being an NMOS transistor;
- a second transistor having a source terminal receiving the feedback voltage, a gate terminal receiving a second non-overlapping pulse signal, and a drain terminal coupled to a second terminal of the first capacitive element, said second transistor being a PMOS transistor;
- a third transistor having a drain terminal receiving the feedback voltage, a gate terminal receiving a third non-overlapping pulse signal, and a source terminal coupled to the second terminal of the first capacitive element, said third transistor being an NMOS transistor;
- a fourth transistor having a drain terminal coupled to the second terminal of the first capacitive element, a source terminal coupled to a first supply voltage, and a gate terminal receiving a fourth non-overlapping pulse signal, said fourth transistor being an NMOS transistor;
- a fifth transistor having a source terminal coupled to the first terminal of the first capacitive element, a gate terminal receiving the feedback voltage, and a drain terminal supplying an output voltage signal;
- said fifth transistor being a PMOS transistor;
- a sixth transistor having a drain terminal coupled to the first terminal of the first capacitive element, a gate terminal receiving a fifth non-overlapping pulse signal, and a source terminal supplying the output voltage signal;
- said sixth transistor being an NMOS transistor;
- and
- a seventh transistor having a drain terminal supplying the output voltage signal, a source terminal coupled to the first supply voltage, and a gate terminal receiving the fourth non-overlapping pulse signal, said seventh transistor being an NMOS transistor.
7 more elements
Dependencies are inferred from the claim text.