Enhanced bump pitch scaling

An integrated circuit (IC) device, comprising:

• an IC die configured to be bonded onto an IC routing member;
• and
• a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member,
• wherein a pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of, pads after the IC die is bonded to the IC routing member;
• wherein the offset is given by:
• ΔL=Δα·ΔT·L, where
• ΔL is the offset,
• Δα is a difference between a coefficient of thermal expansion of the IC die and a coefficient of thermal expansion of the IC routing member,
• ΔT is a difference between a temperature at which the IC die is mounted to the IC routing member and room temperature, and
• L is a distance from the contact pad to a center of the IC die and wherein ΔL, Δα, ΔT, and L are each greater than zero.