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US 8,508,047 B2Granted
Buried word line memory integrated circuit system
AssigneeSpansion LLC
InventorMichael Brennan
Life of this patent
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Abstract
An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.
Claims10
An integrated circuit system, comprising:
- a semiconductor substrate;
- buried word lines in the semiconductor substrate, the buried word lines including vertical charge-trapping dielectric layers;
- bit lines further comprising:
- in-substrate portions in the semiconductor substrate, and
- above-substrate portions over the semiconductor substrate;
- and
- conductive channels between the bit lines that are adjacent to the charge-trapping dielectric layers.
4 more elements
An integrated circuit system, comprising:
- a semiconductor substrate;
- a first address line, further comprising:
- a charge-trapping dielectric layer vertically on sidewalls of a trench in the semiconductor substrate,
- a conductive layer on the dielectric layer, and
- a barrier dielectric over the conductive layer;
- second address lines perpendicular to the first address line and partially in the semiconductor substrate to form dual bit locations;
- and
- conductive channels between the second address lines that are adjacent to the charge-trapping dielectric layer.
5 more elements
Dependencies are inferred from the claim text.