Semiconductor package, semiconductor device, and semiconductor module
AssigneeSamsung Electronics Co., Ltd.
InventorJi-Han Ko
Life of this patent
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Abstract
A semiconductor package, a semiconductor device, and a semiconductor module, the semiconductor package including a substrate, the substrate having a plurality of inner pads; a semiconductor chip attached to the substrate, the semiconductor chip being electrically connected to the inner pads; a plurality of lands on the substrate, the plurality of lands being electrically connected to the inner pads; and at least one bypass interconnection on the substrate, wherein the plurality of lands includes a first land and a second land, the bypass interconnection is connected to the first land and the second land, and the first land is spaced apart from the second land by a distance of about three times or greater an average distance between adjacent lands of the plurality of lands.
Claims19
A semiconductor package, comprising:
- a substrate, the substrate having a plurality of inner pads;
- a semiconductor chip attached to the substrate, the semiconductor chip being electrically connected to the inner pads;
- a plurality of lands on the substrate, the plurality of lands being electrically connected to the inner pads;
- at least one bypass interconnection on the substrate;
- a lower substrate attached to the substrate, the lower substrate having lower lands respectively corresponding to the plurality of lands;
- and
- a lower semiconductor chip attached to the lower substrate, wherein:
- the plurality of lands includes a first land and a second land,
- the bypass interconnection is connected to the first land and the second land, and
- the first land is spaced apart from the second land by a distance of about three times or greater an average distance between adjacent lands of the plurality of lands.
A semiconductor device, comprising:
- a mother board, the mother board having a plurality of substrate lands;
- an upper substrate on the mother board, the upper substrate having a plurality of inner pads;
- a semiconductor chip attached to the upper substrate, the semiconductor chip being electrically connected to the inner pads;
- a plurality of upper lands on the upper substrate, the plurality of upper lands being electrically connected to the inner pads and the substrate lands;
- and
- at least one upper bypass interconnection on the upper substrate, wherein:
- the plurality of upper lands includes a first upper land and a second upper land,
- the at least one upper bypass interconnection is connected to the first upper land and the second upper land, and
- the first upper land is spaced apart from the second upper land by a distance of about three times or greater an average distance between adjacent upper lands of the plurality of upper lands.
Dependencies are inferred from the claim text.