Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump

A packaged semiconductor device, comprising:

• a semiconductor chip package substrate;
• a plurality of solder bumps;
• a semiconductor die that connects to the semiconductor chip package substrate through the plurality of solder bumps;
• a plurality of conductive bond pads formed upon a surface of the semiconductor die that each receives one of the plurality of solder bumps;
• a plurality of topographical features formed upon the surface of the semiconductor die, each of the plurality of topographical features proximate one of the plurality of conductive bond pads, wherein a gap of a predetermined amount separates each topographical feature from a conductive bond pad proximate thereto, and wherein each topographical feature is formed upon the surface of the semiconductor die at a location that is slightly beyond a perimeter of one of the plurality of solder bumps;
• and
• a non-conductive layer disposed over the semiconductor die and the plurality of conductive bond pads and the plurality of topographical features, wherein a thickness of the non-conductive layer beyond an edge of each of the plurality of conductive bond pads is enhanced from the thickness of the non-conductive layer disposed over the conductive bond pad by the presence of one of the plurality of topographical features proximate thereto.

A structure, comprising:

• at least one solder bump;
• a semiconductor die;
• at least one conductive bond pad formed upon a surface of the semiconductor die to receive the at least one solder bump;
• a topographical feature formed upon the surface of the semiconductor die proximate the at least one conductive bond pad, wherein a gap of a predetermined amount separates the topographical feature from the at least one conductive bond pad, wherein the topographical feature is formed upon the surface of the semiconductor die at a location that is slightly beyond a perimeter of the at least one solder bump, and wherein the topographical feature comprises a first topographical feature and a second topographical feature separated a predetermined distance away from the first topographical feature, wherein the first topographical feature is aligned vertically to coincide underneath an edge of the at least one solder bump and the second topographical feature is disposed at a location that is slightly beyond a perimeter of the edge of the at least one solder bump that vertically coincides with the first topographical feature;
• and
• a non-conductive layer disposed over the semiconductor die and the at least one conductive bond pad and the topographical feature, wherein a thickness of the non-conductive layer beyond an edge of the at least one conductive bond pad is enhanced from the thickness of the non-conductive layer disposed over the at least one conductive bond pad by the presence of the topographical feature.