US 8,508,041 B2Granted

Bonding method for three-dimensional integrated circuit and three-dimensional integrated circuit thereof

AssigneeNational Chiao Tung University

InventorsKuan-Neng Chen, Sheng-Yao Hsu

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Abstract

The present invention discloses a bonding method for a three-dimensional integrated circuit and the three-dimensional integrated circuit thereof. The bonding method comprises the steps of: providing a substrate; depositing a film layer on the substrate; providing a light source to light onto the film layer to form a graphic structure; forming a metal co-deposition layer by a first metal and a second metal that are co-deposited on the film layer; providing a first integrated circuit having the substrate, the film layer and the metal co-deposition layer sequentially; providing a second integrated circuit that having the metal co-deposition layer, the film layer and the substrate sequentially; and the first integrated circuit is bonded with the second integrated circuit at a predetermined temperature to form a three-dimensional integrated circuit.

Claims9

Dependent claims

A three-dimensional integrated circuit, comprising:

a first integrated circuit, comprising:
a first substrate;
a first film layer, formed on the first substrate, having a first pattern structure formed thereon;
and
a first metal co-deposition layer disposed on the first film layer, having a first metal and a second metal deposited therewithin;
and
a second integrated circuit, comprising:
a second substrate;
a second film layer, formed on the second substrate, having a second pattern structure formed thereon;
and
a second metal co-deposition layer disposed on the second film layer, having the first metal and the second metal deposited therewithin;
wherein the second integrated circuit is superimposed onto the first integrated circuit at a predetermined temperature, such that the first metal co-deposition layer and the second metal co-deposition layer are bonded with each other, and at least a portion of atoms of the first metal diffuse toward a bonding interface between the first metal co-deposition layer and the second metal co-deposition layer, and at least a portion of atoms of the second metal diffuse toward the respective film layers of each of the integrated circuits to form adhesion and barrier layers for the first metal.

9 more elements

Dependencies are inferred from the claim text.