Chip package structure and package substrate

#1. Field of the Invention

#The present invention relates to a chip packaging technology, and more particularly, to a package substrate and a chip package structure employing such the package substrate.

#2. Description of Related Art

#FIG. 1A is a cross-sectional view of a chip package structure according to one embodiment of the present invention.

#FIG. 1B is a bottom view of the package substrate of FIG. 1A.

#FIG. 2 is a cross-sectional view of a chip package structure according to another embodiment of the present invention.

#FIG. 1A is a cross-sectional view of a chip package structure according to one embodiment of the present invention. FIG. 1B is a bottom view of the package substrate of FIG. 1A. Referring to FIG. 1A, the chip package structure 20 includes a package substrate 100 and a chip 200 assembled to the package substrate 100. In particular, in the present embodiment, the package substrate 100 or the chip package structure 20 having the chip 200 assembled thereto are adapted to be disposed on a carrier 10. This carrier 10 is, for example, a carrier for delivery of the package substrate 100 or the chip package structure 20 during the packaging process.

#The package substrate 100 includes a laminated layer 110, a patterned conductive layer 120, a solder-mask layer 130, at least one outer pad 140 (a plurality of pads 140 are illustrated in FIG. 1A), and a padding pattern 150 (two padding patterns 150 are illustrated in FIG. 1A). The laminated layer 110 has a first surface 112 and a second surface 114 opposite to the first surface 112. In the present embodiment, the laminated layer 110 is formed by a plurality of patterned conductive layers 113 and a plurality of dielectric layers 115 alternatingly laminated with each other, and the patterned conductive layers 113 are electrically connected to one another through at least one conductive via 117.

#The outer patterned conductive layer 120 is disposed on the first surface 112 of the laminated layer 110, and the outer patterned conductive layer 120 includes at least one inner pad 122 (a plurality of pads 122 are illustrated in FIG. 1A). The solder-mask layer 130 is disposed on the first surface 112 of the laminated layer 110, and the solder-mask layer 130 has at least one opening 132 (a plurality of openings 132 are illustrated in FIG. 1A). The inner pads 122 are exposed from these openings 132, respectively. These outer pads 140 are disposed on the solder-mask layer 130 and within these corresponding openings 132, respectively. The outer pads 140 are physically and electrically connected to the inner pads 122 exposed from the corresponding openings 132, respectively.