Fin profile structure and method of making same

A FinFET device comprising:

• a first semiconductor fin over a semiconductor substrate, the first semiconductor fin comprising:
• a first upper section having a first inner side and a first outer side, the first inner side and the first outer side separated by a first width, and the first inner side and the first outer side being orthogonal to a top surface of the semiconductor substrate;
• and
• a first lower section having a second inner side and a second outer side, the second inner side having a first slope, the second outer side having a second slope, the first slope being greater than the second slope, the second inner side and the second outer side are separated by a second width at a top area of the first lower section, and the second inner side and the second outer side are separated by a third width at a bottom area of the first lower section, the third width greater than the second width, and the third width greater than the first width;
• a second semiconductor fin over the semiconductor substrate, the second semiconductor fin comprising:
• a second upper section having a third inner side and a third outer side, the third outer side being the side nearest the first inner side, the third inner side and the third outer side separated by a fourth width, and the third inner side and the third outer side being orthogonal to the top surface of the semiconductor substrate;
• and
• a second lower section having a fourth inner side and a fourth outer side, the fourth inner side and the fourth outer side having a third slope, the fourth inner side and the fourth outer side are separated by a fifth width at a top area of the second lower section, and the fourth inner side and the fourth outer side are separated by a sixth width at a bottom area of the second lower section, the sixth width being greater than the fifth width, the sixth width being greater than the fourth width, and the sixth width being less than the third width;
• a gate dielectric over the first outer side, a first top surface, and the first inner side of the first semiconductor fin, and the gate dielectric over the third outer side, a second top surface, and the third inner side of the second semiconductor fin;
• and
• a gate electrode over the gate dielectric.