Block contact plugs for MOS devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSey-Ping Sun, Chih-Hao Chang, Chao-An Jong, Tsung-Lin Lee, Chung-Ju Lee, Chin-Hsiang Lin
Life of this patent
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Abstract
An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
Claims13
An integrated circuit structure comprising:
- a semiconductor substrate;
- a gate stack overlying the semiconductor substrate;
- a gate spacer on a sidewall of the gate stack;
- a first contact plug comprising an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack;
- a second contact plug over and contacting the first contact plug, wherein the second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact;
- a source/drain region in the semiconductor substrate and adjacent to the sidewall of the gate stack wherein the source/drain region is adjoining an inner corner of the first contact plug;
- and
- a silicide region over the source/drain region, wherein the first contact plug comprises a bottom surface contacting the silicide region.
An integrated circuit structure comprising:
- a semiconductor substrate having an active region;
- a shallow trench isolation (STI) region in the semiconductor substrate and outside the active region;
- a gate stack overlying the active region of the semiconductor substrate;
- a gate spacer on a sidewall of the gate stack and overlying the active region of the semiconductor substrate;
- a source/drain region in the active region of the semiconductor substrate and between the gate stack and the STI region;
- a silicide region on the source/drain region and between the gate spacer and the STI region;
- a first dielectric layer overlying at least a part of the STI region, wherein the first dielectric layer comprises a top surface level with a top surface of the gate spacer;
- a first contact plug in the first dielectric layer and contacting the silicide region, wherein the first contact plug comprises an inner edge contacting a sidewall of the gate spacer wherein the source/drain region is adjoining an inner corner of the first contact plug;
- a second dielectric layer overlying the first dielectric layer and at least a part of the first contact plug;
- and
- a second contact plug in the second dielectric layer and contacting the first contact plug.
Dependencies are inferred from the claim text.