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US 8,507,992 B2Granted
High-K metal gate CMOS
AssigneeInternational Business Machines Corporation
InventorsRenee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
Life of this patent
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Abstract
A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.
Claims12
A semiconductor device comprising:
- a substrate comprising a first device region and a second device region;
- an n-type conductivity digital device present in the first device region comprising a first digital gate structure having at least a first digital device high-k dielectric present atop a first silicon surface of the substrate and at least one rare earth metal present atop the first digital device high-k dielectric, wherein an edge of the first digital device high-k dielectric is aligned with an edge of the at least one rare earth metal, and an n-type analog conductivity device having a first analog gate structure with at least a first analog device high-k dielectric present atop a second silicon surface, wherein a thickness of an first analog gate dielectric structure including the first analog device high-k dielectric of the n-type analog conductivity device is greater than a thickness of first digital gate dielectric structure including the first digital device high-k dielectric of the n-type conductivity digital device, wherein an edge of the first analog gate dielectric structure is horizontally offset from an edge of an overlying gate conductor of the first analog gate structure;
- and
- a p-type conductivity digital device present in the second device region comprising a second digital gate structure having a second digital device high-k dielectric, the second digital gate structure atop a first device channel including a Ge-containing layer, wherein the first high-k dielectric digital device has a greater charge than the second digital device high-k dielectric, wherein an edge of the second digital device high-k dielectric is aligned with an edge of an overlying gate conductor of the second digital gate structure, and a p-type analog conductivity device having a second analog gate structure with at least a second analog device high-k dielectric present atop a second device channel of a Ge-containing layer, wherein a thickness of a second analog gate dielectric structure including the second analog device high-k dielectric of the p-type analog conductivity device is greater than a thickness of second digital gate dielectric structure including the second digital device high-k dielectric of the p-type conductivity digital device, wherein an edge of the second analog gate dielectric structure is horizontally offset from an edge of an overlying gate conductor of the second analog gate structure.
1 more element
A semiconductor device comprising:
- a substrate including a first portion composed of semiconductor devices each having a gate structure including a gate dielectric of a first thickness, and a second portion composed of a semiconductor devices each having a gate structure including a gate dielectric of a second thickness, wherein the second thickness is greater than the first thickness, wherein the gate dielectric of the first thickness has an edge that is aligned with an edge of an overlying gate conductor of the gate structure in the first portion of the substrate, and wherein the gate dielectric of the second thickness has an edge that is horizontally offset from an edge of an overlying gate conductor of the gate structure in the second portion of the substrate;
- n-type device regions present in each of the first portion and the second portion of the substrate, the semiconductor devices present in the n-type device regions include a first digital device and a first analog device each including a gate structure composed of at least one rare earth metal;
- and
- p-type device regions present in each of the first portion and the second portion of the substrate, the semiconductor devices present in the p-type device regions include a second digital device and a second analog device each comprising a device channel including a Ge-containing layer.
1 more element
Dependencies are inferred from the claim text.